arXiv:2510.23346cs.LG2025-10NeurIPS

通过块对角LoRA设计,实现无通信开销的多适配器并行推理。

Block-Diagonal LoRA for Eliminating Communication Overhead in Tensor Parallel LoRA Serving

  • 将LoRA因子约束为块对角结构,避免跨设备通信
  • 在8张A100上实现最高1.79倍端到端加速
  • 适配器参数减少约14%仍保持性能,适合大规模服务场景

同时服务多个LoRA适配器时,传统方法需合并权重导致交换开销且无法批处理。S-LoRA虽通过张量并行分片缓解此问题,但仍存在实际通信开销。本文提出块对角LoRA,强制部分因子为块对角形式,使适配器分片与基模型张量并行完全对齐,无需额外通信。实验表明,该方法在参数效率上与标准LoRA相当(相同参数量下性能相近),在8张A100 GPU上对Llama-3.1-70B实现最高1.79倍(平均1.23倍)端到端加速,适配器参数仅需0.87倍;对Llama-3.1-8B实现最高1.63倍(平均1.3倍)加速,参数仅需0.86倍。结果显著优于S-LoRA。

原文摘要 · Abstract (English)

When serving a single base LLM with several different LoRA adapters simultaneously, the adapters cannot simply be merged with the base model's weights as the adapter swapping would create overhead and requests using different adapters could not be batched. Rather, the LoRA computations have to be separated from the base LLM computations, and in a multi-device setup the LoRA adapters can be sharded in a way that is well aligned with the base model's tensor parallel execution, as proposed in S-LoRA. However, the S-LoRA sharding strategy encounters some communication overhead, which may be small in theory, but can be large in practice. In this paper, we propose to constrain certain LoRA factors to be block-diagonal, which allows for an alternative way of sharding LoRA adapters that does not require any additional communication for the LoRA computations. We demonstrate in extensive experiments that our block-diagonal LoRA approach is similarly parameter efficient as standard LoRA (i.e., for a similar number of parameters it achieves similar downstream performance) and that it leads to significant end-to-end speed-up over S-LoRA. For example, when serving on eight A100 GPUs, we observe up to 1.79x (1.23x) end-to-end speed-up with 0.87x (1.74x) the number of adapter parameters for Llama-3.1-70B, and up to 1.63x (1.3x) end-to-end speed-up with 0.86x (1.73x) the number of adapter parameters for Llama-3.1-8B.

LoRA张量并行推理优化通信开销

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