基于RISC-V的FPGA芯片，专为脉冲神经网络加速设计。
FeNN-DMA: A RISC-V SoC for SNN acceleration
- 采用可编程RISC-V架构，适配脉冲神经网络计算特点。
- 单核支持1.6万神经元、2.56亿突触，性能达当前顶尖水平。
- 适合需要复杂神经元模型和高能效的类脑计算研究者。
脉冲神经网络（SNNs）是低功耗的有前景替代方案，尤其适用于时空任务如关键词识别与视频分类。但其算术强度远低于传统人工神经网络（ANNs），难以匹配标准加速器如GPU和TPU。现场可编程门阵列（FPGAs）适合内存密集型负载，本文提出一种新型全可编程RISC-V系统级芯片（FeNN-DMA），专为现代UltraScale+ FPGA上的SNN仿真而设计。结果表明，FeNN-DMA在资源占用和能耗上与现有固定功能SNN加速器相当，却支持更复杂的神经元模型与网络结构，并可实现每核16,000个神经元、2.56亿个突触的仿真规模。基于此能力，我们在Spiking Heidelberg Digits、Neuromorphic MNIST和Braille触觉分类任务中实现了最先进的分类准确率。
原文摘要 · Abstract (English)
Spiking Neural Networks (SNNs) are a promising, energy-efficient alternative to standard Artificial Neural Networks (ANNs) and are particularly well-suited to spatio-temporal tasks such as keyword spotting and video classification. However, SNNs have a much lower arithmetic intensity than ANNs and are therefore not well-matched to standard accelerators like GPUs and TPUs. Field Programmable Gate Arrays (FPGAs) are designed for such memory-bound workloads, and here we present a novel, fully-programmable RISC-V-based system-on-chip (FeNN-DMA), tailored to simulating SNNs on modern UltraScale+ FPGAs. We show that FeNN-DMA has comparable resource usage and energy requirements to state-of-the-art fixed-function SNN accelerators, yet it supports more complex neuron models and network topologies, and can simulate up to 16 thousand neurons and 256 million synapses per core. Using this functionality, we demonstrate state-of-the-art classification accuracy on the Spiking Heidelberg Digits, Neuromorphic MNIST and Braille tactile classification tasks.
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