用时间域计算提升时序机器推理效率，大幅降低功耗与延迟。
Event-Driven Digital-Time-Domain Inference Architectures for Tsetlin Machines
- 通过延迟累积机制替代传统算术运算，实现低功耗推理。
- 在多类分类中，能量效率提升数个数量级，吞吐量显著增加。
- 适合边缘设备部署，尤其适用于对能效要求高的实时系统。
机器学习通过拟合模型参数来近似输入输出映射关系，以预测未知样本。然而，这些模型在推理阶段通常需要大量算术运算，导致延迟高、功耗大。本文提出一种面向时序机器（Tsetlin Machine, TM）推理过程的数字时间域计算架构，以应对上述挑战。该方法利用延迟累积机制，缓解类别求和带来的高昂算术开销，并采用获胜者通吃（Winner-Takes-All）策略替代传统幅度比较器。具体而言，针对多类时序机器，设计了基于汉明距离的时间域方案；同时，结合差分延迟路径与首位检测器对数压缩时间域方案，解决了二进制符号与指数级延迟累积问题。与功能等价的后端实现数字时序机器架构相比，所提架构在能效和吞吐量上均实现数量级提升。
原文摘要 · Abstract (English)
Machine learning fits model parameters to approximate input-output mappings, predicting unknown samples. However, these models often require extensive arithmetic computations during inference, increasing latency and power consumption. This paper proposes a digital-time-domain computing approach for Tsetlin machine (TM) inference process to address these challenges. This approach leverages a delay accumulation mechanism to mitigate the costly arithmetic sums of classes and employs a Winner-Takes-All scheme to replace conventional magnitude comparators. Specifically, a Hamming distance-driven time-domain scheme is implemented for multi-class TMs. Furthermore, differential delay paths, combined with a leading-ones-detector logarithmic delay compression digital-time-domain scheme, are utilised for the coalesced TMs, accommodating both binary-signed and exponential-scale delay accumulation issues. Compared to the functionally equivalent, post-implementation digital TM architecture baseline, the proposed architecture demonstrates orders-of-magnitude improvements in energy efficiency and throughput.
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