用动态执行行为提升电路表示学习，助力验证与优化
DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior
- 基于操作级控制数据流图建模电路动态行为
- 在6300个设计上实现更高精度的分支命中与翻转率预测
- 可迁移至功耗估计和断言预测，适合芯片验证工程师
现有图神经网络（GNN）多关注电路静态特性，难以捕捉运行时行为，影响电路验证与优化。为此，我们提出DR-GNN（DynamicRTL-GNN），通过操作级控制数据流图（CDFG）建模寄存器传输级（RTL）电路，融合静态结构与多周期执行行为，以捕捉动态依赖关系和运行时执行模式。为训练与评估该模型，我们构建了首个综合性动态电路数据集，包含超过6,300个Verilog设计及63,000条仿真轨迹。实验表明，DR-GNN在分支命中预测和翻转率预测任务上优于现有模型；其学习到的表示还能有效迁移到相关动态任务中，在功耗估计与断言预测上取得优异性能。
原文摘要 · Abstract (English)
There is a growing body of work on using Graph Neural Networks (GNNs) to learn representations of circuits, focusing primarily on their static characteristics. However, these models fail to capture circuit runtime behavior, which is crucial for tasks like circuit verification and optimization. To address this limitation, we introduce DR-GNN (DynamicRTL-GNN), a novel approach that learns RTL circuit representations by incorporating both static structures and multi-cycle execution behaviors. DR-GNN leverages an operator-level Control Data Flow Graph (CDFG) to represent Register Transfer Level (RTL) circuits, enabling the model to capture dynamic dependencies and runtime execution. To train and evaluate DR-GNN, we build the first comprehensive dynamic circuit dataset, comprising over 6,300 Verilog designs and 63,000 simulation traces. Our results demonstrate that DR-GNN outperforms existing models in branch hit prediction and toggle rate prediction. Furthermore, its learned representations transfer effectively to related dynamic circuit tasks, achieving strong performance in power estimation and assertion prediction.
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