将FPGA嵌入SPAD图像传感器，实现像素级动态重构与低功耗事件处理。
Reconfigurable, large-format D-ToF/photon-counting SPAD image sensors with embedded FPGA for scene adaptability
- SPAD像素旁集成可编程FPGA，支持实时逻辑重构。
- 通过查找表实现加权求和，降低功耗并简化接口。
- 支持神经网络的动态重配置，适合复杂场景自适应。
CMOS兼容的单光子雪崩二极管（SPAD）因其具备光子数分辨和计数能力，已成为许多系统中相机的首选方案。作为原生数字光学接口，SPAD天然适合现场逻辑处理与事件驱动计算，通常需外接FPGA实现可重构性。本文提出将FPGA直接集成在SPAD芯片上，实现像素或像素簇级别的紧密耦合。为验证该架构可行性，设计了一种基于查找表的可编程加权求和机制，用于处理时间戳与光子计数。输出采用类似FPGA的分层处理方式，显著降低功耗并简化输入输出。最后，展示了如何高效利用查找表构建并重配置人工神经网络。
原文摘要 · Abstract (English)
CMOS-compatible single-photon avalanche diodes (SPADs) have emerged in many systems as the solution of choice for cameras with photon-number resolution and photon counting capabilities. Being natively digital optical interfaces, SPADs are naturally drawn to in situ logic processing and event-driven computation; they are usually coupled to discrete FPGAs to enable reconfigurability. In this work, we propose to bring the FPGA on-chip, in direct contact with the SPADs at pixel or cluster level. To demonstrate the suitability of this approach, we created an architecture for processing timestamps and photon counts using programmable weighted sums based on an efficient use of look-up tables. The outputs are processed hierarchically, similarly to what is done in FPGAs, reducing power consumption and simplifying I/Os. Finally, we show how artificial neural networks can be designed and reprogrammed by using look-up tables in an efficient way.
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