用难度预测调度多个大模型，省钱提效生成更准的硬件代码。
VeriDispatcher: Multi-Model Dispatching through Pre-Inference Difficulty Prediction for RTL Generation Optimization
- 提前预测任务难易度，智能分配给最合适的模型
- 在两个数据集上提升18%准确率，商用调用减少60%
- 适合需要低成本高质量硬件生成的工程团队
大型语言模型在硬件描述语言（RTL）生成中表现优异，但不同模型因架构和训练差异，在不同任务上各有优势。现有方法多依赖单个模型提示或微调，未充分研究如何协调多个不同模型以共同提升质量并降低消耗。本文提出VeriDispatcher框架，通过预推理难度预测，将任务动态分配给最适配的LLM组合。针对每个模型，基于任务描述的语义嵌入训练轻量分类器，使用结合语法、结构相似性和功能正确性的基准变体生成难度评分。推理时，该框架利用预测器选择性地路由任务至少数模型。在10种不同模型上测试，于RTLLM数据集实现最高18%的准确率提升，仅使用40%的商用调用；在VerilogEval上保持准确率，商用调用减少25%，实现高性价比的LLM在硬件自动化设计中的部署。
原文摘要 · Abstract (English)
Large Language Models (LLMs) show strong performance in RTL generation, but different models excel on different tasks because of architecture and training differences. Prior work mainly prompts or finetunes a single model. What remains not well studied is how to coordinate multiple different LLMs so they jointly improve RTL quality while also reducing cost, instead of running all models and choosing the best output. We define this as the multi-LLM RTL generation problem. We propose VeriDispatcher, a multi-LLM RTL generation framework that dispatches each RTL task to suitable LLMs based on pre-inference difficulty prediction. For each model, we train a compact classifier over semantic embeddings of task descriptions, using difficulty scores derived from benchmark variants that combine syntax, structural similarity, and functional correctness. At inference, VeriDispatcher uses these predictors to route tasks to a selected subset of LLMs. Across 10 diverse LLMs on RTLLM and VerilogEval, VeriDispatcher achieves up to 18% accuracy improvement on RTLLM using only 40% of commercial calls, and on VerilogEval maintains accuracy while reducing commercial usage by 25%, enabling cost-effective, high-quality LLM deployment in hardware design automation.
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