用迁移学习从网表预测布局性能，提升早期设计优化能力
ParaGate: Parasitic-Driven Domain Adaptation Transfer Learning for Netlist Performance Prediction
- 分三步走：先预训练预测寄生参数，再用EDA工具做时序分析，最后全局校准
- 在openE906数据集上，到达时间预测的R²从0.119提升至0.897
- 只需少量微调数据，适合芯片设计早期阶段快速评估
传统EDA流程中，版图级性能指标仅在布局布线后才能获取，限制了早期阶段的全局优化。尽管已有基于神经网络的方法可直接从网表预测版图性能，但因商业布局布线工具的黑箱启发式规则导致设计间数据差异大，泛化能力受限。为此，本文提出ParaGate，一种三阶段跨阶段预测框架，从网表推断版图级时序与功耗。首先采用两阶段迁移学习预测寄生参数：在中等规模电路上预训练，再在更大电路上微调以捕捉极端条件。其次，依赖EDA工具进行时序分析，将长路径数值推理任务交由工具完成。最后，利用子图特征进行全局校准。实验表明，ParaGate仅需少量微调数据即可实现强泛化性能：在openE906数据集上，到达时间预测的R²由0.119提升至0.897。结果证明，ParaGate可为综合与布局阶段提供全局优化指导。
原文摘要 · Abstract (English)
In traditional EDA flows, layout-level performance metrics are only obtainable after placement and routing, hindering global optimization at earlier stages. Although some neural-network-based solutions predict layout-level performance directly from netlists, they often face generalization challenges due to the black-box heuristics of commercial placement-and-routing tools, which create disparate data across designs. To this end, we propose ParaGate, a three-step cross-stage prediction framework that infers layout-level timing and power from netlists. First, we propose a two-phase transfer-learning approach to predict parasitic parameters, pre-training on mid-scale circuits and fine-tuning on larger ones to capture extreme conditions. Next, we rely on EDA tools for timing analysis, offloading the long-path numerical reasoning. Finally, ParaGate performs global calibration using subgraph features. Experiments show that ParaGate achieves strong generalization with minimal fine-tuning data: on openE906, its arrival-time R2 from 0.119 to 0.897. These results demonstrate that ParaGate could provide guidance for global optimization in the synthesis and placement stages.
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