VeriPy用Python一键生成SDR硬件加速器，无需懂硬件设计。
VeriPy -- A New Python-Based Approach for SDR Pipelined/Unrolled Hardware Accelerator Generation
- 基于Python的高阶综合工具，自动生成流水线与展开架构。
- 生成代码频率提升70%，资源消耗略高但接近手写水平。
- 适合无硬件背景的通信工程师快速部署高性能SDR加速器。
软件定义无线电（SDR）在通信领域发挥重要作用，可根据需求灵活定制通信系统。为提升SDR应用性能，近年广泛采用硬件加速器。然而，现有高阶综合（HLS）工具对通信工程师不友好，缺乏针对其使用场景的专门支持。为此，本文提出基于Python的HLS工具VeriPy，可为SDR设计生成主流的流水线与展开式硬件加速器，无需掌握数字硬件知识或硬件描述语言（HDL）。VeriPy支持自动测试平台生成、随机输入激励、可扩展硬件库、性能与资源估算，并具备算法与硬件层面双重优化潜力。相比使用指令优化的Vivado HLS设计，VeriPy生成的硬件在时钟频率上最高可提升70%，资源消耗稍高，但性能与资源消耗与手写实现相当。代码复杂度方面，VeriPy无需使用指令（pragma），完全规避低层硬件知识要求；对于简单算法，输入代码长度与Vivado HLS相近。
原文摘要 · Abstract (English)
Software-defined radio (SDR) plays an important role in the communication field by providing a flexible and customized communication system for different purposes according to the needs. To enhance the performance of SDR applications, hardware accelerators have been widely deployed in recent years. In facing this obstacle, a necessity arises for a high-level synthesis (HLS) tool specifically designed for communication engineers without detailed hardware knowledge. To lower the barrier between SDR engineers and hardware development, this work proposed a Python-based HLS tool, VeriPy, which can generate both mainstream architecture for hardware accelerators in Verilog specifically for SDR designs including unrolled design and pipelined design, requiring no detailed digital hardware knowledge or Hardware Description Languages (HDL). Furthermore, VeriPy supports automatic testbench generation with random input stimulus, an extensible hardware library, performance and resource estimation, and offers strong optimisation potential at both the algorithmic and digital hardware levels. The generated hardware design by VeriPy can achieve up to 70% faster operating frequency compared to pragma-optimised Vivado HLS designs with a reasonably higher resource con-sumption while delivering comparable performance and resource consumption to hand-coded implementations. Regarding code complexity, VeriPy requires no pragmas, completely eliminating the need for low-level hardware knowledge. For straightforward algorithms, the input code length remains comparable to that of Vivado HLS.
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