用智能电路分块与强化学习，提升芯片测试生成效率。
InF-ATPG: Intelligent FFR-Driven ATPG with Advanced Circuit Representation Guided Reinforcement Learning
- 将电路分为无扇出区域，结合专用特征增强强化学习模型
- 相比传统方法减少55.06%回溯次数，故障覆盖更优
- 适合芯片设计验证与自动化测试团队快速部署
自动测试图案生成（ATPG）是集成电路设计与测试中的关键环节，负责高效生成测试模式。随着半导体技术发展，传统ATPG在实现预期故障覆盖率时面临执行时间过长的问题，影响芯片上市周期。近年来，强化学习（RL）和图神经网络（GNN）虽展现潜力，但存在奖励延迟和电路表征不足等缺陷。本文提出InF-ATPG，一种基于先进电路表示的智能FFR驱动ATPG框架，通过将电路划分为无扇出区域（FFRs），并引入ATPG特有特征至新型QGNN架构，显著提升测试图案生成效率。实验结果表明，InF-ATPG平均比传统方法减少55.06%的回溯次数，比机器学习方法减少38.31%，同时提升故障覆盖率。
原文摘要 · Abstract (English)
Automatic test pattern generation (ATPG) is a crucial process in integrated circuit (IC) design and testing, responsible for efficiently generating test patterns. As semiconductor technology progresses, traditional ATPG struggles with long execution times to achieve the expected fault coverage, which impacts the time-to-market of chips. Recent machine learning techniques, like reinforcement learning (RL) and graph neural networks (GNNs), show promise but face issues such as reward delay in RL models and inadequate circuit representation in GNN-based methods. In this paper, we propose InF-ATPG, an intelligent FFR-driven ATPG framework that overcomes these challenges by using advanced circuit representation to guide RL. By partitioning circuits into fanout-free regions (FFRs) and incorporating ATPG-specific features into a novel QGNN architecture, InF-ATPG enhances test pattern generation efficiency. Experimental results show InF-ATPG reduces backtracks by 55.06\% on average compared to traditional methods and 38.31\% compared to the machine learning approach, while also improving fault coverage.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。