手把手教你怎么从RISC-V核搭出高效低功耗神经形态处理器。
From RISC-V Cores to Neuromorphic Arrays: A Tutorial on Building Scalable Digital Neuromorphic Processors
- 用可扩展的RISC-V核阵列加简单网络芯片，逐步构建神经形态架构。
- 通过专用神经处理单元和循环控制器，降低控制开销并提升能效。
- 适合想设计自研神经形态芯片的学生和工程师，重点讲架构权衡与加速思路。
数字神经形态处理器正成为低功耗、始终在线的边缘AI应用的有前途计算平台。本文以SENECA平台为实例，系统阐述全数字神经形态处理器的核心架构设计原则。从由小型RISC-V处理核构成的灵活阵列，通过简单片上网络（NoC）互联开始，逐步演化：从基础事件驱动的全连接网络实现，到引入专用神经处理单元（NPEs）和循环控制器，将细粒度控制从通用核中卸载。过程中讨论了如脉冲分组、事件驱动深度优先卷积、高分辨率事件视觉中的硬注意力处理等软件与映射技术。重点分析架构权衡、性能与能耗瓶颈，并强调利用灵活性逐步添加领域专用加速。本文假设读者具备基本神经形态概念（脉冲、事件驱动计算、稀疏激活）和深度神经网络工作负载知识，不提供新实验结果，而是整合并诠释我们之前关于SENECA的研究成果，为希望自主设计数字神经形态处理器的学生与实践者提供清晰、渐进的架构视角。
原文摘要 · Abstract (English)
Digital neuromorphic processors are emerging as a promising computing substrate for low-power, always-on EdgeAI applications. In this tutorial paper, we outline the main architectural design principles behind fully digital neuromorphic processors and illustrate them using the SENECA platform as a running example. Starting from a flexible array of tiny RISC-V processing cores connected by a simple Network-on-Chip (NoC), we show how to progressively evolve the architecture: from a baseline event-driven implementation of fully connected networks, to versions with dedicated Neural Processing Elements (NPEs) and a loop controller that offloads fine-grained control from the general-purpose cores. Along the way, we discuss software and mapping techniques such as spike grouping, event-driven depth-first convolution for convolutional networks, and hard-attention style processing for high-resolution event-based vision. The focus is on architectural trade-offs, performance and energy bottlenecks, and on leveraging flexibility to incrementally add domain-specific acceleration. This paper assumes familiarity with basic neuromorphic concepts (spikes, event-driven computation, sparse activation) and deep neural network workloads. It does not present new experimental results; instead, it synthesizes and contextualizes findings previously reported in our SENECA publications to provide a coherent, step-by-step architectural perspective for students and practitioners who wish to design their own digital neuromorphic processors.
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