用生成式AI快速精准预测芯片热分布,助力早期设计优化。
2D-ThermAl: Physics-Informed Framework for Thermal Analysis of Circuits using Generative AI
- 结合物理规律与U-Net结构,从电路活动直接生成温度图。
- 误差仅0.71°C,速度比传统仿真快200倍。
- 适用于大芯片早期热风险检测,支持高温场景泛化。
现代集成电路中,非均匀功耗和高密度晶体管导致温度骤升与可靠性问题。传统基于有限元法(FEM)的仿真虽准确但计算成本过高,难以用于早期设计阶段,常需多次迭代修改以解决后期热故障。为此,我们提出ThermAl——一种融合物理约束的生成式AI框架,可直接从输入活动轮廓识别热源,并估计全芯片瞬态与稳态热分布。该模型采用增强型混合U-Net架构,引入位置编码与玻尔兹曼正则化,确保物理一致性。训练数据来自COMSOL生成的多样化热耗散图,涵盖从简单逻辑门(如反相器、NAND、XOR)到复杂电路的设计。实验表明,ThermAl在大型电路上实现精确温度映射,均方根误差(RMSE)仅为0.71°C,且运行速度比传统FEM工具快约200倍。我们在多种布局与负载下评估性能,验证其在大规模EDA流程中的适用性。尽管热可靠性评估通常需覆盖85°C以上,本研究聚焦早期热点检测与热模式学习。为保证模型在25–95°C范围内的泛化能力,我们在扩展数据集上进行交叉验证,即使在峰值功耗与应力场景下,仍保持小于2.2%全量程的RMSE,证明其在极端条件下的高精度表现。
原文摘要 · Abstract (English)
Thermal analysis is increasingly critical in modern integrated circuits, where non-uniform power dissipation and high transistor densities can cause rapid temperature spikes and reliability concerns. Traditional methods, such as FEM-based simulations offer high accuracy but computationally prohibitive for early-stage design, often requiring multiple iterative redesign cycles to resolve late-stage thermal failures. To address these challenges, we propose 'ThermAl', a physics-informed generative AI framework which effectively identifies heat sources and estimates full-chip transient and steady-state thermal distributions directly from input activity profiles. ThermAl employs a hybrid U-Net architecture enhanced with positional encoding and a Boltzmann regularizer to maintain physical fidelity. Our model is trained on an extensive dataset of heat dissipation maps, ranging from simple logic gates (e.g., inverters, NAND, XOR) to complex designs, generated via COMSOL. Experimental results demonstrate that ThermAl delivers precise temperature mappings for large circuits, with a root mean squared error (RMSE) of only 0.71°C, and outperforms conventional FEM tools by running up to ~200 times faster. We analyze performance across diverse layouts and workloads, and discuss its applicability to large-scale EDA workflows. While thermal reliability assessments often extend beyond 85°C for post-layout signoff, our focus here is on early-stage hotspot detection and thermal pattern learning. To ensure generalization beyond the nominal operating range 25-55°C, we additionally performed cross-validation on an extended dataset spanning 25-95°C maintaining a high accuracy (<2.2% full-scale RMSE) even under elevated temperature conditions representative of peak power and stress scenarios.
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