小模型+智能体在硬件设计中逼近大模型效果
David vs. Goliath: Can Small Models Win Big with Agentic AI in Hardware Design?
- 用小模型配合智能体工作流完成任务分解与纠错
- 在CVDP基准上实现接近大模型性能，成本降低显著
- 适合资源有限但需高效迭代的芯片设计场景
大语言模型推理需要大量算力和能耗，使领域特定任务成本高昂且不可持续。随着基础模型不断扩展，我们提出疑问：硬件设计是否必须依赖大模型？本文通过在NVIDIA的综合Verilog设计问题（CVDP）基准上评估小语言模型与定制化智能体框架的组合，发现智能体工作流——通过任务分解、迭代反馈与修正——不仅以极低成本实现了接近大模型的性能，还为智能体自身提供了学习机会，为复杂设计任务中的高效、自适应解决方案开辟了新路径。
原文摘要 · Abstract (English)
Large Language Model(LLM) inference demands massive compute and energy, making domain-specific tasks expensive and unsustainable. As foundation models keep scaling, we ask: Is bigger always better for hardware design? Our work tests this by evaluating Small Language Models coupled with a curated agentic AI framework on NVIDIA's Comprehensive Verilog Design Problems(CVDP) benchmark. Results show that agentic workflows: through task decomposition, iterative feedback, and correction - not only unlock near-LLM performance at a fraction of the cost but also create learning opportunities for agents, paving the way for efficient, adaptive solutions in complex design tasks.
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