用FPGA加速模型恢复，提升实时系统性能6.3倍
Hardware Software Optimizations for Fast Model Recovery on Reconfigurable Architectures
- 将模型恢复重构为流水线数据流，减少同步开销
- 在典型负载下比基线少6.3倍周期数，实现实时处理
- 适合对延迟敏感的物理AI与数字孪生场景
模型恢复（MR）是物理人工智能和实时数字孪生的核心技术，但GPU常因迭代依赖、内核启动开销、内存带宽利用率低及数据传输延迟高而效率低下。本文提出MERINDA，一种基于FPGA的MR加速框架，将计算重构为流式数据流管道。通过片上局部性优化，包括BRAM分块、定点核函数以及同时使用LUT阵列与进位链加法器，充分暴露细粒度空间并行性，同时最小化片外通信。该硬件感知设计消除了同步瓶颈，在迭代更新中保持高吞吐。在典型MR工作负载下，MERINDA相比FPGA基线LTC最多减少6.3倍周期数，使时间敏感的物理系统达到实时性能。
原文摘要 · Abstract (English)
Model Recovery (MR) is a core primitive for physical AI and real-time digital twins, but GPUs often execute MR inefficiently due to iterative dependencies, kernel-launch overheads, underutilized memory bandwidth, and high data-movement latency. We present MERINDA, an FPGA-accelerated MR framework that restructures computation as a streaming dataflow pipeline. MERINDA exploits on-chip locality through BRAM tiling, fixed-point kernels, and the concurrent use of LUT fabric and carry-chain adders to expose fine-grained spatial parallelism while minimizing off-chip traffic. This hardware-aware formulation removes synchronization bottlenecks and sustains high throughput across the iterative updates in MR. On representative MR workloads, MERINDA delivers up to 6.3x fewer cycles than an FPGA-based LTC baseline, enabling real-time performance for time-critical physical systems.
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