让AI通过实验测试理解硬件设计，提升验证能力
DUET: Agentic Design Understanding via Experimentation and Testing
- AI生成假设并用EDA工具反复测试，逐步构建设计认知
- 在形式化验证任务中，性能优于无实验的基线方法
- 适合需要深入理解复杂硬件设计的开发者和研究者
基于大语言模型的AI代理在解决复杂软件工程问题上表现良好，但在硬件设计任务中表现不佳。寄存器传输级（RTL）代码使用SystemVerilog低层语法表达复杂的动态时序行为，仅靠语法难以让LLM推断其行为，限制了代码补全、文档生成和验证等下游任务。为此，我们提出DUET：一种通过实验与测试实现设计理解的通用方法。DUET模仿硬件专家的认知过程，不依赖单次阅读RTL，而是通过迭代生成假设，利用EDA工具（如仿真、波形检查、形式化验证）进行测试，并整合结果建立自下而上的设计理解。评估表明，相比无实验的基线流程，DUET显著提升了AI代理在形式化验证任务中的表现。
原文摘要 · Abstract (English)
AI agents powered by large language models (LLMs) are being used to solve increasingly complex software engineering challenges, but struggle with hardware design tasks. Register Transfer Level (RTL) code presents a unique challenge for LLMs, as it encodes complex, dynamic, time-evolving behaviors using the low-level language features of SystemVerilog. LLMs struggle to infer these complex behaviors from the syntax of RTL alone, which limits their ability to complete all downstream tasks like code completion, documentation, or verification. In response to this issue, we present DUET: a general methodology for developing Design Understanding via Experimentation and Testing. DUET mimics how hardware design experts develop an understanding of complex designs: not just via a one-off readthrough of the RTL, but via iterative experimentation using a number of tools. DUET iteratively generates hypotheses, tests them with EDA tools (e.g., simulation, waveform inspection, and formal verification), and integrates the results to build a bottom-up understanding of the design. In our evaluations, we show that DUET improves AI agent performance on formal verification, when compared to a baseline flow without experimentation.
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