arXiv:2512.06854cs.ARcs.AI2025-12NeurIPS被引 1

首个开源的现代CPU架构级功耗建模数据集,助力高效精准功耗预测。

ArchPower: Dataset for Architecture-Level Power Modeling of Modern CPU Design

  • 基于真实设计流程收集25种配置下8个负载的200组数据
  • 每条数据含100+特征与11个组件的细粒度功耗标签
  • 适合芯片设计、ML功耗建模研究者快速验证算法

功耗是大规模集成电路尤其是复杂现代处理器(即CPU)的主要设计目标。准确评估CPU功耗需经历耗时数月的完整IC实现流程。在早期设计阶段(如架构级),传统功耗模型精度差。近年虽有基于机器学习的架构级功耗模型提升精度,但数据可用性成严重挑战。目前尚无开源数据集支持此重要应用。典型数据集生成需正确实现CPU设计并重复执行功耗仿真流程,耗费大量设计经验、工程投入和时间。即便企业内部私有数据集也常无法反映真实设计场景。本文提出ArchPower,首个开源的架构级处理器功耗建模数据集。我们通过复杂且真实的全流程设计,采集了CPU架构信息作为特征,以及真实仿真得到的功耗作为标签。数据集包含200个样本,来自25种不同CPU配置在8种工作负载下的运行结果。每个样本包含超过100个架构特征,涵盖硬件与事件参数。标签提供细粒度功耗信息,包括总设计功耗及11个组件的功耗,每项功耗进一步分解为组合逻辑、时序逻辑、存储器和时钟四类。ArchPower已在https://github.com/hkust-zhiyao/ArchPower发布。

原文摘要 · Abstract (English)

Power is the primary design objective of large-scale integrated circuits (ICs), especially for complex modern processors (i.e., CPUs). Accurate CPU power evaluation requires designers to go through the whole time-consuming IC implementation process, easily taking months. At the early design stage (e.g., architecture-level), classical power models are notoriously inaccurate. Recently, ML-based architecture-level power models have been proposed to boost accuracy, but the data availability is a severe challenge. Currently, there is no open-source dataset for this important ML application. A typical dataset generation process involves correct CPU design implementation and repetitive execution of power simulation flows, requiring significant design expertise, engineering effort, and execution time. Even private in-house datasets often fail to reflect realistic CPU design scenarios. In this work, we propose ArchPower, the first open-source dataset for architecture-level processor power modeling. We go through complex and realistic design flows to collect the CPU architectural information as features and the ground-truth simulated power as labels. Our dataset includes 200 CPU data samples, collected from 25 different CPU configurations when executing 8 different workloads. There are more than 100 architectural features in each data sample, including both hardware and event parameters. The label of each sample provides fine-grained power information, including the total design power and the power for each of the 11 components. Each power value is further decomposed into four fine-grained power groups: combinational logic power, sequential logic power, memory power, and clock power. ArchPower is available at https://github.com/hkust-zhiyao/ArchPower.

功耗建模数据集CPU设计机器学习

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