用查表神经网络加速量子比特读取，大幅降低资源与延迟。
LUNA: LUT-Based Neural Architecture for Fast and Low-Cost Qubit Readout
- 用积分器降维+查表逻辑实现轻量神经网络
- 面积减少10.95倍，延迟降低30%且保真度几乎不变
- 适合需要高速低延迟的量子纠错系统
量子比特读取是量子计算中的关键操作，将量子比特的模拟响应映射为离散的经典状态。近年来，深度神经网络（DNN）被用于提升读取精度。但现有基于DNN的硬件实现资源消耗大、推理延迟高，难以满足低延迟解码和量子误差校正（QEC）环路的需求。本文提出LUNA，一种基于查表（LUT）的快速高效超导量子比特读取加速器，结合低成本积分器预处理与查表神经网络进行分类。该架构采用简单积分器实现维度压缩，硬件开销极小；并利用LogicNets（由DNN合成的LUT逻辑）显著降低资源占用，实现超低延迟推理。我们还引入基于差分进化的设计探索与优化框架，寻找高质量设计点。结果表明，相比最先进方案，LUNA在面积上最多减少10.95倍，延迟降低30%，同时保真度几乎无损失。LUNA实现了可扩展、低占地、高速的量子比特读取，助力更大更可靠的量子计算系统发展。
原文摘要 · Abstract (English)
Qubit readout is a critical operation in quantum computing systems, which maps the analog response of qubits into discrete classical states. Deep neural networks (DNNs) have recently emerged as a promising solution to improve readout accuracy . Prior hardware implementations of DNN-based readout are resource-intensive and suffer from high inference latency, limiting their practical use in low-latency decoding and quantum error correction (QEC) loops. This paper proposes LUNA, a fast and efficient superconducting qubit readout accelerator that combines low-cost integrator-based preprocessing with Look-Up Table (LUT) based neural networks for classification. The architecture uses simple integrators for dimensionality reduction with minimal hardware overhead, and employs LogicNets (DNNs synthesized into LUT logic) to drastically reduce resource usage while enabling ultra-low-latency inference. We integrate this with a differential evolution based exploration and optimization framework to identify high-quality design points. Our results show up to a 10.95x reduction in area and 30% lower latency with little to no loss in fidelity compared to the state-of-the-art. LUNA enables scalable, low-footprint, and high-speed qubit readout, supporting the development of larger and more reliable quantum computing systems.
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