用AI模型加速芯片网络设计，预测最优参数
Artificial Intelligence-Driven Network-on-Chip Design Space Exploration: Neural Network Architectures for Design
- 用神经网络预测芯片网络参数，替代传统慢速仿真
- 扩散模型预测误差最小，均方误差达0.463
- 设计探索速度提升数个数量级，适合快速芯片开发
芯片网络（NoC）设计需在高维配置空间中探索，以满足严格的吞吐量和延迟要求。传统方法效率低，难以处理复杂非线性参数交互。本文提出一种基于机器学习的自动化设计空间探索框架，结合BookSim仿真与反向神经网络模型。对比了多层感知机（MLP）、条件扩散模型和条件变分自编码器（CVAE）三种架构，在不同网状拓扑下生成超过15万条仿真数据。条件扩散模型表现最佳，对未见数据的均方误差（MSE）为0.463。该框架将设计探索时间大幅缩短数个数量级，为快速可扩展的NoC协同设计提供了实用方案。
原文摘要 · Abstract (English)
Network-on-Chip (NoC) design requires exploring a high-dimensional configuration space to satisfy stringent throughput requirements and latency constraints. Traditional design space exploration techniques are often slow and struggle to handle complex, non-linear parameter interactions. This work presents a machine learning-driven framework that automates NoC design space exploration using BookSim simulations and reverse neural network models. Specifically, we compare three architectures - a Multi-Layer Perceptron (MLP),a Conditional Diffusion Model, and a Conditional Variational Autoencoder (CVAE) to predict optimal NoC parameters given target performance metrics. Our pipeline generates over 150,000 simulation data points across varied mesh topologies. The Conditional Diffusion Model achieved the highest predictive accuracy, attaining a mean squared error (MSE) of 0.463 on unseen data. Furthermore, the proposed framework reduces design exploration time by several orders of magnitude, making it a practical solution for rapid and scalable NoC co-design.
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