用图对比学习和强化学习优化FPGA加速器的编译流程
DAPO: Design Structure-Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning
- 从控制与数据流图中提取程序语义信息
- 相比Vitis HLS平均提升2.36倍运行速度
- 适合需要高效定制化编译的硬件加速设计
高层次综合（HLS）工具广泛应用于基于FPGA的领域专用加速器设计。然而，现有工具依赖于源自软件编译的固定优化策略，限制了其效果。针对特定设计定制优化策略需要深层语义理解、准确的硬件指标估算以及先进的搜索算法——这些能力当前方法尚不具备。我们提出DAPO，一种面向设计结构的优化步骤排序框架，通过从控制流与数据流图中提取程序语义，采用对比学习生成丰富嵌入，并利用解析模型实现精准硬件指标估算。这些组件协同指导强化学习代理发现适配具体设计的优化策略。在经典HLS设计上的评估表明，我们的端到端流程相比Vitis HLS平均提升2.36倍性能。
原文摘要 · Abstract (English)
High-Level Synthesis (HLS) tools are widely adopted in FPGA-based domain-specific accelerator design. However, existing tools rely on fixed optimization strategies inherited from software compilations, limiting their effectiveness. Tailoring optimization strategies to specific designs requires deep semantic understanding, accurate hardware metric estimation, and advanced search algorithms -- capabilities that current approaches lack. We propose DAPO, a design structure-aware pass ordering framework that extracts program semantics from control and data flow graphs, employs contrastive learning to generate rich embeddings, and leverages an analytical model for accurate hardware metric estimation. These components jointly guide a reinforcement learning agent to discover design-specific optimization strategies. Evaluations on classic HLS designs demonstrate that our end-to-end flow delivers a 2.36 speedup over Vitis HLS on average.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。