KANELÉ让可学习分段函数神经网络在FPGA上实现超快低耗推理。
KANELÉ: Kolmogorov-Arnold Networks for Efficient LUT-based Evaluation
- 用可学习的一维样条函数替代传统神经元，天然适配FPGA查找表映射。
- 相比之前方法提速最高达2700倍，资源节省数个数量级。
- 适合实时控制等对延迟和功耗敏感的嵌入式场景。
在要求实时响应与低功耗的应用中，FPGA上的低延迟、高效率神经网络推理至关重要。基于查找表（LUT）的神经网络是一种常见方案，兼具强大的表达能力与高效的FPGA实现。本文提出KANELÉ框架，利用柯尔莫哥洛夫-阿诺德网络（KANs）的独特性质实现FPGA部署。与传统多层感知机（MLPs）不同，KANs采用具有固定定义域的可学习一维样条作为边激活函数，其结构天然适合离散化和高效LUT映射。我们首次系统性地设计了KAN在FPGA上的实现流程，联合优化训练、量化与剪枝，以构建紧凑、高吞吐、低延迟的KAN架构。实验表明，相较先前的KAN-FPGA方法，性能提升最高达2700倍，资源消耗降低数个数量级。同时，KANELÉ在多个主流基准测试中表现持平或超越其他基于LUT的架构，尤其在涉及符号或物理公式的任务中优势显著，且能在FPGA硬件间均衡资源使用。最后，我们通过将其拓展至实时、低功耗控制系统，验证了该框架的通用性。
原文摘要 · Abstract (English)
Low-latency, resource-efficient neural network inference on FPGAs is essential for applications demanding real-time capability and low power. Lookup table (LUT)-based neural networks are a common solution, combining strong representational power with efficient FPGA implementation. In this work, we introduce KANELÉ, a framework that exploits the unique properties of Kolmogorov-Arnold Networks (KANs) for FPGA deployment. Unlike traditional multilayer perceptrons (MLPs), KANs employ learnable one-dimensional splines with fixed domains as edge activations, a structure naturally suited to discretization and efficient LUT mapping. We present the first systematic design flow for implementing KANs on FPGAs, co-optimizing training with quantization and pruning to enable compact, high-throughput, and low-latency KAN architectures. Our results demonstrate up to a 2700x speedup and orders of magnitude resource savings compared to prior KAN-on-FPGA approaches. Moreover, KANELÉ matches or surpasses other LUT-based architectures on widely used benchmarks, particularly for tasks involving symbolic or physical formulas, while balancing resource usage across FPGA hardware. Finally, we showcase the versatility of the framework by extending it to real-time, power-efficient control systems.
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