arXiv:2601.04382cs.GRcs.CV2026-01被引 1

在图处理器上实现全片上内存的辐射泡沫体渲染,支持近实时帧率。

Radiant Foam Rendering on a Graph Processor

  • 将场景分片部署于各核心本地内存,通过分层路由传递光线,保持计算局部性。
  • 640x480分辨率下达到约1帧/秒,图像与深度图质量接近原GPU实现。
  • 为未来分布式内存加速器优化不规则数据密集型渲染提供关键瓶颈分析。

许多新兴的多核加速器用数百到数千个轻量级核心替代单一大容量设备内存,每个核心仅拥有少量本地SRAM,并通过显式片上通信交换数据。这种架构虽具备高聚合带宽,但打破了体积渲染技术的关键假设:即光线可随机访问统一的大场景表示。因此在该类硬件上高效渲染需同时分布数据与计算,尽量保持光线遍历的局部性,并将通信结构化为可预测路径。本文提出一种完全基于片上SRAM的分布式渲染系统,用于Graphcore Mk2 IPU(智能处理单元)上的Radiant Foam Voronoi单元体积表示。系统将场景分片至各计算单元,通过分层路由叠加网络在分片间传递光线,实现完全从片上SRAM进行光线步进,且通信路径可预测。在Mip-NeRF~360场景上,系统在640x480分辨率下达到约1帧/秒的近交互吞吐率,图像与深度图质量接近原基于GPU的Radiant Foam实现,且所有场景数据和光线状态均保留在片上SRAM中。本工作不仅验证了可行性,还分析了路由、内存与调度瓶颈,为未来分布式内存加速器更好支持不规则、高数据移动的渲染负载提供了指导。

原文摘要 · Abstract (English)

Many emerging many-core accelerators replace a single large device memory with hundreds to thousands of lightweight cores, each owning only a small local SRAM and exchanging data via explicit on-chip communication. This organization offers high aggregate bandwidth, but it breaks a key assumption behind many volumetric rendering techniques: that rays can randomly access a large, unified scene representation. Rendering efficiently on such hardware therefore requires distributing both data and computation, keeping ray traversal mostly local, and structuring communication into predictable routes. We present a fully in-SRAM, distributed renderer for the Radiant Foam Voronoi-cell volumetric representation on the Graphcore Mk2 IPU(Intelligence Processing Unit), a many-core accelerator with tile-local SRAM and explicit inter-tile communication. Our system shards the scene across tiles and forwards rays between shards through a hierarchical routing overlay, enabling ray marching entirely from on-chip SRAM with predictable communication. On Mip-NeRF~360 scenes, the system attains near-interactive throughput of approximately 1 fps at 640x480 with image and depth map quality close to the original GPU-based Radiant Foam implementation, while keeping all scene data and ray state in on-chip SRAM. Beyond demonstrating feasibility, we analyze routing, memory, and scheduling bottlenecks that inform how future distributed-memory accelerators can better support irregular, data-movement-heavy rendering workloads.

体积渲染图处理器片上内存分布式渲染

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