用大模型自动生成并调试硬件测试用例，提升发现和定位设计缺陷的效率。
LAUDE: LLM-Assisted Unit Test Generation and Debugging of Hardware DEsigns
- 结合大模型推理与代码语义理解，生成高精度测试用例。
- 在组合/时序电路中分别检测到100%和93%的缺陷，成功调试93%和84%。
- 适合硬件验证工程师、自动化测试研究者使用。
单元测试在硬件设计生命周期中至关重要，用于确保模块功能正确并符合规范。然而，编写覆盖多种设计特性的测试用例需要深入理解设计逻辑并具备创造力。当测试暴露设计缺陷时，调试工程师需诊断、定位并修复问题，这一过程往往耗时费力。本文提出LAUDE，一个统一的硬件设计单元测试生成与调试框架，融合大语言模型（LLM）的链式思维（CoT）推理能力与设计源码的语义理解。通过提示工程与设计执行信息结合，提升测试生成准确率与可调试性。我们在VerilogEval数据集上的大量有缺陷硬件代码中应用了闭源与开源大模型，结果显示，生成的测试用例在组合电路中检测到100%的缺陷，在时序电路中检测到93%；在组合与时序电路中分别成功调试了93%和84%的缺陷。
原文摘要 · Abstract (English)
Unit tests are critical in the hardware design lifecycle to ensure that component design modules are functionally correct and conform to the specification before they are integrated at the system level. Thus developing unit tests targeting various design features requires deep understanding of the design functionality and creativity. When one or more unit tests expose a design failure, the debugging engineer needs to diagnose, localize, and debug the failure to ensure design correctness, which is often a painstaking and intense process. In this work, we introduce LAUDE, a unified unit-test generation and debugging framework for hardware designs that cross-pollinates the semantic understanding of the design source code with the Chain-of-Thought (CoT) reasoning capabilities of foundational Large-Language Models (LLMs). LAUDE integrates prompt engineering and design execution information to enhance its unit test generation accuracy and code debuggability. We apply LAUDE with closed- and open-source LLMs to a large corpus of buggy hardware design codes derived from the VerilogEval dataset, where generated unit tests detected bugs in up to 100% and 93% of combinational and sequential designs and debugged up to 93% and 84% of combinational and sequential designs, respectively.
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