通过结构与连接优化，让LUT神经网络更省资源、更快推理。
Enhancing LUT-based Deep Neural Networks Inference through Architecture and Connectivity Optimization
- 用加法器聚合多个子神经元，大幅减少LUT用量
- 在不增加开销的前提下，精度提升最高达2.13%
- 适合部署在FPGA等资源受限设备上的高效模型
将深度神经网络（DNN）部署于FPGA等资源受限的边缘设备时，需在延迟、功耗和硬件资源之间取得平衡，同时保持高精度。现有基于查找表（LUT）的DNN（如LogicNets、PolyLUT、NeuraLUT）面临两大挑战：LUT规模呈指数级增长，以及随机稀疏连接效率低下。本文提出SparseLUT框架，通过两种正交优化解决这些问题。首先，提出一种架构增强方法，通过加法器聚合多个PolyLUT子神经元，使LUT消耗降低2.0x–13.9x，推理延迟降低1.2x–1.6x，同时保持相近精度。在此基础上，进一步引入非贪婪训练算法，通过选择性剪枝低贡献输入并策略性重连高价值连接，优化神经元连接。该训练优化无额外面积与延迟开销，在多个基准测试中持续提升精度：在MNIST上最高提升2.13%，在Jet Substructure Classification任务上提升0.94%。
原文摘要 · Abstract (English)
Deploying deep neural networks (DNNs) on resource-constrained edge devices such as FPGAs requires a careful balance among latency, power, and hardware resource usage, while maintaining high accuracy. Existing Lookup Table (LUT)-based DNNs -- such as LogicNets, PolyLUT, and NeuraLUT -- face two critical challenges: the exponential growth of LUT size and inefficient random sparse connectivity. This paper presents SparseLUT, a comprehensive framework that addresses these challenges through two orthogonal optimizations. First, we propose an architectural enhancement that aggregates multiple PolyLUT sub-neurons via an adder, significantly reducing LUT consumption by 2.0x-13.9x and lowering inference latency by 1.2x-1.6x, all while maintaining comparable accuracy. Building upon this foundation, we further introduce a non-greedy training algorithm that optimizes neuron connectivity by selectively pruning less significant inputs and strategically regrowing more effective ones. This training optimization, which incurs no additional area and latency overhead, delivers consistent accuracy improvements across benchmarks -- achieving up to a 2.13% gain on MNIST and 0.94% on Jet Substructure Classification compared to existing LUT-DNN approaches.
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