用时间编码直接路由脉冲,实现超快低功的神经形态计算。
Polychronous Wave Computing: Timing-Native Address Selection in Spiking Networks
- 基于脉冲时间相位编码,通过干涉仪并行计算多模板相关性。
- 在强静态失配下,硬件闭环调校使门电路准确率从55.9%提升至97.2%。
- 适合光子、极化子等平台上的稀疏路由任务,如专家混合模型选择。
脉冲时间提供了组合式地址空间,表明基于时间的脉冲推理可作为查找与路由执行,而非密集乘加运算。然而,多数类脑与光子系统仍将事件数字化为时间戳、分箱或频率,再通过时钟逻辑进行选择。本文提出多时序波计算(Polychronous Wave Computing, PWC),一种原生时间的地址选择机制,将相对脉冲延迟直接映射到波域中的离散输出路径。脉冲时间在旋转参考系中以相位编码,并由可编程多端口干涉仪并行评估K个模板的相关性;驱动-耗散的竞争胜者通吃阶段完成物理argmax,输出单热码端口。我们推导了相位包裹与互相干带来的工作范围限制,并将定时抖动、静态相位失配与去相干合并为单一有效相位噪声预算,其诱导的胜者-亚军差距可预测边界优先失败,提供仅依赖强度的校准目标。仿真显示,非线性竞争相比噪声线性强度读出显著提升路由保真度;硬件在环相位调校使强静态失配下的时间顺序门准确率从55.9%恢复至97.2%。PWC为查找表式脉冲网络及稀疏Top-1门(如专家混合路由)提供高速路由协处理器,适用于极化子、光子及振荡器平台。
原文摘要 · Abstract (English)
Spike timing offers a combinatorial address space, suggesting that timing-based spiking inference can be executed as lookup and routing rather than as dense multiply--accumulate. Yet most neuromorphic and photonic systems still digitize events into timestamps, bins, or rates and then perform selection in clocked logic. We introduce Polychronous Wave Computing (PWC), a timing-native address-selection primitive that maps relative spike latencies directly to a discrete output route in the wave domain. Spike times are phase-encoded in a rotating frame and processed by a programmable multiport interferometer that evaluates K template correlations in parallel; a driven--dissipative winner-take-all stage then performs a physical argmax, emitting a one-hot output port. We derive the operating envelope imposed by phase wrapping and mutual coherence, and collapse timing jitter, static phase mismatch, and dephasing into a single effective phase-noise budget whose induced winner--runner-up margin predicts boundary-first failures and provides an intensity-only calibration target. Simulations show that nonlinear competition improves routing fidelity compared with noisy linear intensity readout, and that hardware-in-the-loop phase tuning rescues a temporal-order gate from 55.9% to 97.2% accuracy under strong static mismatch. PWC provides a fast routing coprocessor for LUT-style spiking networks and sparse top-1 gates (e.g., mixture-of-experts routing) across polaritonic, photonic, and oscillator platforms.
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