用图神经网络精准预测电路映射延迟，提升时序优化效果
GNN-based Path-aware multi-view Circuit Learning for Technology Mapping
- 融合AIG功能编码、技术映射结构与关键路径信息，多视角学习电路延迟
- 在19个EPFL基准上，相比传统方法平均降低19.9%延迟，优于现有SOTA模型
- 适合需要高精度时序优化的集成电路设计工程师使用
传统技术映射依赖抽象的、与工艺无关的延迟模型，导致时序估计系统性偏差。为解决此问题，本文提出GPA（基于图神经网络的路径感知多视角电路学习）框架，通过融合三种互补电路结构视图——基于与非门图（AIGs）的功能编码、映射后技术单元的结构特征以及关键时序路径信息——实现数据驱动的精确延迟预测。GPA仅在工业级映射网表的关键路径真实单元延迟数据上训练，能以极高精度分类切割延迟，直接指导更优映射决策。在19个EPFL组合逻辑基准上，GPA相比传统启发式方法（techmap, MCH）和先前最先进的基于机器学习的方法SLAP，分别实现19.9%、2.1%和4.1%的平均延迟降低，且不牺牲面积效率。
原文摘要 · Abstract (English)
Traditional technology mapping suffers from systemic inaccuracies in delay estimation due to its reliance on abstract, technology-agnostic delay models that fail to capture the nuanced timing behavior behavior of real post-mapping circuits. To address this fundamental limitation, we introduce GPA(graph neural network (GNN)-based Path-Aware multi-view circuit learning), a novel GNN framework that learns precise, data-driven delay predictions by synergistically fusing three complementary views of circuit structure: And-Inverter Graphs (AIGs)-based functional encoding, post-mapping technology emphasizes critical timing paths. Trained exclusively on real cell delays extracted from critical paths of industrial-grade post-mapping netlists, GPA learns to classify cut delays with unprecedented accuracy, directly informing smarter mapping decisions. Evaluated on the 19 EPFL combinational benchmarks, GPA achieves 19.9%, 2.1% and 4.1% average delay reduction over the conventional heuristics methods (techmap, MCH) and the prior state-of-the-art ML-based approach SLAP, respectively-without compromising area efficiency.
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