Aeon通过神经符号记忆管理，让大模型长时推理更高效稳定。
Aeon: High-Performance Neuro-Symbolic Memory Management for Long-Horizon LLM Agents
- 用记忆宫殿和事件图构建分层记忆结构，提升上下文组织能力。
- 实现3.1倍压缩与5.6倍计算加速，读取延迟低至亚微秒级。
- 适合需要长期记忆的AI代理系统，如复杂任务规划与对话引擎。
大语言模型受限于自注意力的二次计算开销及‘中间遗忘’现象，随着上下文窗口扩展，推理能力下降。现有基于向量数据库的扁平化RAG架构将记忆视为无结构嵌入集合，无法捕捉长周期交互的层次与时间结构。本文提出Aeon——一种神经符号认知操作系统，将记忆重构为受控的系统资源。其核心由记忆宫殿（基于Atlas的SIMD加速页聚类向量索引）与事件轨迹（神经符号情景图）构成。该架构实现三项突破：(1) 对称INT8标量量化，利用NEON SDOT指令实现3.1倍空间压缩与5.6倍数学加速；(2) 解耦写前日志（WAL），在统计上几乎无开销（<1%）下保障崩溃可恢复性；(3) 侧车块区（Sidecar Blob Arena）通过追加只读mmap文件与代际垃圾回收，消除此前440字符文本上限。语义旁路缓冲器（SLB）利用对话局部性，实现亚5微秒检索延迟，且在缓存插入时将INT8向量反量化为FP32以保持一级缓存内查找性能。在Apple M4 Max上的基准测试显示，整体架构实现4.70纳秒的INT8点积延迟，10万节点树遍历耗时3.09微秒（较FP32快3.4倍），在16线程高压竞争下仍保持750纳秒的P99读取延迟，通过基于时段的回收机制实现。
原文摘要 · Abstract (English)
Large Language Models (LLMs) are fundamentally constrained by the quadratic computational cost of self-attention and the "Lost in the Middle" phenomenon, where reasoning capabilities degrade as context windows expand. Existing solutions, primarily "Flat RAG" architectures relying on vector databases, treat memory as an unstructured bag of embeddings, failing to capture the hierarchical and temporal structure of long-horizon interactions. This paper presents Aeon, a Neuro-Symbolic Cognitive Operating System that redefines memory as a managed OS resource. Aeon structures memory into a Memory Palace (a spatial index implemented via Atlas, a SIMD-accelerated Page-Clustered Vector Index) and a Trace (a neuro-symbolic episodic graph). This architecture introduces three advances: (1) Symmetric INT8 Scalar Quantization, achieving 3.1x spatial compression and 5.6x math acceleration via NEON SDOT intrinsics; (2) a decoupled Write-Ahead Log (WAL) ensuring crash-recoverability with statistically negligible overhead (<1%); and (3) a Sidecar Blob Arena eliminating the prior 440-character text ceiling via an append-only mmap-backed blob file with generational garbage collection. The Semantic Lookaside Buffer (SLB) exploits conversational locality to achieve sub-5us retrieval latencies, with INT8 vectors dequantized to FP32 on cache insertion to preserve L1-resident lookup performance. Benchmarks on Apple M4 Max demonstrate that the combined architecture achieves 4.70ns INT8 dot product latency, 3.09us tree traversal at 100K nodes (3.4x over FP32), and P99 read latency of 750ns under hostile 16-thread contention via epoch-based reclamation.
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