用统一架构实现多种精度的高效神经网络计算
SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency
- 通过分层复用模块，避免重复设计硬件路径
- 在多种精度下实现45%以上资源节省，能效提升显著
- 适合边缘AI设备部署，兼顾精度与效率
边缘AI系统对算术单元的精度、能效和硬件紧凑性提出更高要求。正位数（Posit）通过分段精度、宽动态范围和更强的数值鲁棒性优于浮点和定点表示。本文提出SPADE，一种支持Posit (8,0)、Posit (16,1)和Posit (32,2)的统一多精度SIMD乘加架构。不同于以往单精度或浮点/定点的SIMD MAC，SPADE引入了基于模式感知的通道融合式SIMD正位数数据通路，层次化复用正位数特有子模块（LOD、补码器、移位器、乘法器），无需重复数据通路即可覆盖8/16/32位精度。Xilinx Virtex-7 FPGA实现显示，对Posit (8,0)减少45.13%的LUT和80%的slice；对Posit (16,1)和Posit (32,2)分别提升28.44%和17.47%；多精度支持仅增加6.9% LUT和14.9%寄存器开销。在TSMC各工艺节点的ASIC结果中，达到1.38 GHz主频与6.1 mW功耗（28 nm）。在MNIST、CIFAR-10/100及字母数据集上的评估表明推理精度具有竞争力。
原文摘要 · Abstract (English)
The growing demand for edge-AI systems requires arithmetic units that balance numerical precision, energy efficiency, and compact hardware while supporting diverse formats. Posit arithmetic offers advantages over floating- and fixed-point representations through its tapered precision, wide dynamic range, and improved numerical robustness. This work presents SPADE, a unified multi-precision SIMD Posit-based multiplyaccumulate (MAC) architecture supporting Posit (8,0), Posit (16,1), and Posit (32,2) within a single framework. Unlike prior single-precision or floating/fixed-point SIMD MACs, SPADE introduces a regime-aware, lane-fused SIMD Posit datapath that hierarchically reuses Posit-specific submodules (LOD, complementor, shifter, and multiplier) across 8/16/32-bit precisions without datapath replication. FPGA implementation on a Xilinx Virtex-7 shows 45.13% LUT and 80% slice reduction for Posit (8,0), and up to 28.44% and 17.47% improvement for Posit (16,1) and Posit (32,2) over prior work, with only 6.9% LUT and 14.9% register overhead for multi-precision support. ASIC results across TSMC nodes achieve 1.38 GHz at 6.1 mW (28 nm). Evaluation on MNIST, CIFAR-10/100, and alphabet datasets confirms competitive inference accuracy.
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