用模块化设计实现可配置的随机神经元，大幅节省硬件资源。
Configurable p-Neurons Using Modular p-Bits
- 分离信号与输入路径，构建可插拔的模块化p-bit
- 支持多种概率激活函数，实测硬件开销降低10倍
- 适合低功耗边缘计算和类脑芯片设计
概率比特（p-bits）近年被用于神经网络中作为具有逻辑激活函数的随机神经元。然而，尚有大量未探索的概率激活函数。本文通过将p-bit的随机信号路径与输入数据路径解耦，重构出模块化p-bit，实现了可配置的概率神经元（p-neurons），支持包括逻辑斯蒂、双曲正切和修正线性单元（ReLU）在内的多种概率版本激活函数。我们提出基于自旋电子学（CMOS + sMTJ）的设计，实现宽范围且可调的概率工作区间。最后，在FPGA上实验验证了数字CMOS版本，采用随机单元共享技术，相比传统数字p-bit实现，硬件资源需求减少一个数量级（10倍）。
原文摘要 · Abstract (English)
Probabilistic bits (p-bits) have recently been employed in neural networks (NNs) as stochastic neurons with sigmoidal probabilistic activation functions. Nonetheless, there remain a wealth of other probabilistic activation functions that are yet to be explored. Here we re-engineer the p-bit by decoupling its stochastic signal path from its input data path, giving rise to a modular p-bit that enables the realization of probabilistic neurons (p-neurons) with a range of configurable probabilistic activation functions, including a probabilistic version of the widely used Logistic Sigmoid, Tanh and Rectified Linear Unit (ReLU) activation functions. We present spintronic (CMOS + sMTJ) designs that show wide and tunable probabilistic ranges of operation. Finally, we experimentally implement digital-CMOS versions on an FPGA, with stochastic unit sharing, and demonstrate an order of magnitude (10x) saving in required hardware resources compared to conventional digital p-bit implementations.
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