AI自动将电路图转为网表，准确率超现有方法两倍
SINA: A Circuit Schematic Image-to-Netlist Generator Using Artificial Intelligence
- 用深度学习识别元件，连通性通过连通域标记精确提取
- 整体网表生成准确率达96.47%，比顶尖方法高2.72倍
- 开源全自动系统，适合电子设计自动化研究者使用
当前将电路原理图图像转化为机器可读网表的方法在元件识别和连接关系推断上存在困难。本文提出SINA，一个开源的全自动电路原理图图像到网表生成器。SINA结合深度学习实现精准元件检测，采用连通域标记（CCL）进行精确的连接关系提取，并利用光学字符识别（OCR）获取元件标识符，同时借助视觉-语言模型（VLM）实现可靠的标识符分配。实验表明，SINA的整体网表生成准确率达到96.47%，较现有最先进方法提升2.72倍。
原文摘要 · Abstract (English)
Current methods for converting circuit schematic images into machine-readable netlists struggle with component recognition and connectivity inference. In this paper, we present SINA, an open-source, fully automated circuit schematic image-to-netlist generator. SINA integrates deep learning for accurate component detection, Connected-Component Labeling (CCL) for precise connectivity extraction, and Optical Character Recognition (OCR) for component reference designator retrieval, while employing a Vision-Language Model (VLM) for reliable reference designator assignments. In our experiments, SINA achieves 96.47% overall netlist-generation accuracy, which is 2.72x higher than state-of-the-art approaches.
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