用结构化验证让大模型自动生成可纠错的电路图，无需标准答案。
PCBSchemaGen: Reward-Guided LLM Code Synthesis for Printed Circuit Boards (PCB) Schematic Design with Structured Verification
- 基于芯片数据手册构建领域模式，引导大模型生成符合物理约束的电路图。
- 通过五层连续奖励验证器定位引脚级错误，使31B模型在227个任务中平均通过率81.3%。
- 框架可零修改迁移至不同数据集，适合无标准答案的硬件设计场景。
现有大模型代码合成评测多依赖单元测试作为奖励信号，但印刷电路板（PCB）原理图设计缺乏此类机制：正确性依赖真实芯片封装与引脚分配的结构约束，每项任务无黄金参考，SPICE仿真也无法验证原理图层面的正确性。本文提出PCBSchemaGen，一种无需训练的推理时框架，将冻结的大模型转化为可验证、可修复的原理图生成器。该框架从芯片数据手册中提取领域模式以约束模型解码，结合一个确定性的五层连续奖励验证器（支持引脚级错误定位），并通过汤普森采样强化学习策略优化候选方案。在覆盖227个真实芯片任务、22个统一电路领域的两个基准上评估，相同模型（Gemma-4-31B）平均通过率达81.3%；框架在两个基准间实现零代码修改的迁移能力；而基于类似提示的基线方法在复杂系统级设计中表现崩溃。结果表明，在无单元测试或黄金参考的领域，基于确定性结构验证的推理时优化是通用可行的代码合成范式。相关基准与验证器已开源于https://github.com/HZou9/PCBSchemaGen_v2。
原文摘要 · Abstract (English)
Most LLM code-synthesis benchmarks rely on unit tests as the reward oracle, but PCB schematic design has none: correctness is defined by structured physical constraints over real IC packages and pin-level assignments, per-task golden references are unavailable, and SPICE simulation does not validate schematic-level correctness. We introduce PCBSchemaGen, a training-free inference-time framework that turns a frozen LLM into a verifiable, repairable PCB schematic generator. The framework induces a domain schema from IC datasheets to ground LLM decoding, pairs it with a deterministic 5-layer continuous-reward verifier with pin-level error localization, and refines candidates through a Thompson Sampling arm-acquiring bandit. We evaluate on 2 PCB benchmarks covering 227 real-IC tasks across 22 unified circuit domains, including a public-schematic-derived suite that serves as a fully held-out generalization test (verifier, KG library, and prompts frozen before any evaluation). Under our framework, an open-weight 31B model (Gemma-4-31B) passes 81.3% of PCBBench tasks on average, and the same framework transfers across both benchmarks with zero verifier code changes; a Circuitron-style inference-time prompting baseline on the same Gemma-4-31B backbone collapses on hard system-level designs. This suggests inference-time refinement under a deterministic structural verifier is a general recipe for reference-free LLM code synthesis in domains without unit-test oracles. Our benchmarks and deterministic verifier are publicly available at https://github.com/HZou9/PCBSchemaGen_v2.
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