用可重构模拟器件实现高效非线性神经网络,适合边缘计算。
Physical Analogue Kolmogorov-Arnold Networks based on Reconfigurable Nonlinear-Processing Units
- 用可调电压控制的纳米硅器件模拟非线性函数,替代传统线性层。
- 推理功耗仅200皮焦,延迟0.6微秒,能效比数字模型高100倍。
- 适用于低功耗、小体积的边缘智能设备,硬件友好性强。
Kolmogorov-Arnold网络(KANs)将神经计算从线性层转向可学习的非线性边函数,但其高效硬件实现仍是难题。本文提出基于可重构非线性处理单元(RNPUs)的物理模拟KAN架构:利用多端口纳米硅器件,通过控制电压调节输入输出特性。将多个RNPUs组合为边处理器,并集成混合信号接口,构建可重构模拟KAN(aKAN)系统,实现紧凑的回归与分类任务。基于实验校准的RNPU模型和实测数据,证明其在复杂度递增的任务中仍具高精度函数逼近能力,且参数量少于或相当多层感知机(MLPs)。系统级估算显示,典型负载下单次推理能耗约200 pJ,端到端延迟约0.6 μs,相较同精度数字定点MLP,能效提升超100倍,面积减少超10倍。结果表明RNPUs是可扩展的原生硬件非线性计算单元,模拟KAN架构为节能、低延迟、小尺寸的硅基神经网络硬件提供了可行路径,尤其适合边缘推理场景。
原文摘要 · Abstract (English)
Kolmogorov-Arnold Networks (KANs) shift neural computation from linear layers to learnable nonlinear edge functions, but implementing these nonlinearities efficiently in hardware remains an open challenge. Here we introduce a physical analogue KAN architecture in which edge functions are realized in materia using reconfigurable nonlinear-processing units (RNPUs): multi-terminal nanoscale silicon devices whose input-output characteristics are tuned via control voltages. By combining multiple RNPUs into an edge processor and assembling these blocks into a reconfigurable analogue KAN (aKAN) architecture with integrated mixed-signal interfacing, we establish a realistic system-level hardware implementation that enables compact KAN-style regression and classification with programmable nonlinear transformations. Using experimentally calibrated RNPU models and hardware measurements, we demonstrate accurate function approximation across increasing task complexity while requiring fewer or comparable trainable parameters than multilayer perceptrons (MLPs). System-level estimates indicate an energy per inference of roughly 200 pJ and an end-to-end inference latency of roughly 0.6 $μ$s for a representative workload, corresponding to over 100$\times$ reduction in energy accompanied by $>$10$\times$ reduction in area compared to a digital fixed-point MLP at similar approximation error. These results establish RNPUs as scalable, hardware-native nonlinear computing primitives and identify analogue KAN architectures as a realistic silicon-based pathway toward energy-, latency-, and footprint-efficient analogue neural-network hardware, particularly for edge inference.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品;中文卡片由大模型生成,请以原文为准。