用大模型加速后量子密码硬件设计，提升2.6倍运行速度。
Accelerating Post-Quantum Cryptography via LLM-Driven Hardware-Software Co-Design
- 用大模型分析算法，自动生成FPGA加速器设计
- 相比传统方法，核心计算块提速2.6倍，关键路径更短
- 适合需要快速部署的后量子密码硬件研发团队
后量子密码（PQC）对抵御量子威胁至关重要，但其算法计算复杂，难以高效部署于硬件。本文探索大型语言模型（LLMs）在加速PQC软硬件协同设计中的潜力，聚焦于FALCON数字签名方案。提出一种新框架，利用LLM分析PQC算法，识别性能瓶颈模块，并生成适用于FPGA实现的候选硬件描述。首次对LLM驱动合成与传统高阶综合（HLS）方法在FALCON低层计算密集型核上进行量化对比，结果显示，人机协作的LLM生成加速器可使核执行时间提升最高达2.6倍，关键路径更短，同时揭示了资源利用率与功耗间的权衡。结果表明，LLM能显著降低设计负担和开发周期，通过自动化FPGA加速器迭代，为FPGA上快速、可适应的PQC加速器设计提供新方向。
原文摘要 · Abstract (English)
Post-quantum cryptography (PQC) is crucial for securing data against emerging quantum threats. However, its algorithms are computationally complex and difficult to implement efficiently on hardware. In this paper, we explore the potential of Large Language Models (LLMs) to accelerate the hardware-software co-design process for PQC, with a focus on the FALCON digital signature scheme. We present a novel framework that leverages LLMs to analyze PQC algorithms, identify performance-critical components, and generate candidate hardware descriptions for FPGA implementation. We present the first quantitative comparison between LLM-driven synthesis and conventional HLS-based approaches for low-level compute-intensive kernels in FALCON, showing that human-in-the-loop LLM-generated accelerators can achieve up to 2.6x speedup in kernel execution time with shorter critical paths, while highlighting trade-offs in resource utilization and power consumption. Our results suggest that LLMs can minimize design effort and development time by automating FPGA accelerator design iterations for PQC algorithms, offering a promising new direction for rapid and adaptive PQC accelerator design on FPGAs.
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