让专用硬件大模型与智能推理系统协同，自动生成正确RTL代码。
ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
- 用三组件迭代优化，融合专用模型与通用大模型优势。
- 在CVDP上比14个基线最高提升41.02%的通过率。
- 适合做芯片设计自动化、低代码硬件开发的研究者。
近年来，大语言模型的发展推动了其在硬件设计自动化中的应用，尤其是高精度RTL代码生成。现有工作主要沿两条独立路径：(i) 训练领域适配的RTL模型以内化硬件语义；(ii) 构建基于模拟反馈引导的前沿通用大模型的智能体系统。二者互补但各有局限。本文提出ACE-RTL，通过代理上下文演化（ACE）统一二者。该框架将一个基于170万条RTL样本训练的专用大模型，与前沿推理大模型通过生成器、反思器和协调器三个协同组件结合，迭代优化RTL代码直至功能正确。我们进一步提出并行扩展策略，通过并发探索多种调试路径，显著减少首次成功所需的实际运行时间。在CVDP基准测试中，ACE-RTL相较14个竞争基线最高实现41.02%的通过率提升。
原文摘要 · Abstract (English)
Recent advances in LLMs have sparked growing interest in applying them to hardware design automation, particularly for accurate RTL code generation. Prior efforts follow two largely independent paths: (i) training domain-adapted RTL models to internalize hardware semantics, (ii) developing agentic systems that leverage frontier generic LLMs guided by simulation feedback. However, these two paths exhibit complementary strengths and weaknesses. In this work, we present ACE-RTL that unifies both directions through Agentic Context Evolution (ACE). ACE-RTL integrates an RTL-specialized LLM, trained on a large-scale dataset of 1.7 million RTL samples, with a frontier reasoning LLM through three synergistic components: the generator, reflector, and coordinator. These components iteratively refine RTL code toward functional correctness. We further analyze a parallel scaling strategy that reduces wall-clock iterations to first success by exploring diverse debugging trajectories concurrently. On the CVDP benchmark, ACE-RTL achieves up to a 41.02% pass rate improvement over 14 competitive baselines.
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