用FPGA实现压缩算法，解决单光子传感器数据传输瓶颈
FPGA Implementation of Sketched LiDAR for a 192 x 128 SPAD Image Sensor
- 用多项式样条统计压缩算法替代传统直方图，减少计算开销
- 在192×128像素阵列上实现512倍压缩比，保留深度精度
- 适合高分辨率SPAD成像系统研发人员参考
本研究提出一种基于多项式样条函数的统计压缩算法的高效FPGA实现，旨在应对新兴高空间分辨率单光子雪崩二极管（SPAD）阵列中高达数十吉字节每秒的数据传输带宽挑战。实验表明，该硬件实现相比传统直方图输出可达到512倍压缩比，且具备进一步优化潜力。算法首先通过定点（FXP）运算和查找表（LUTs）在软件中优化，消除显式加法、乘法及非线性操作，实现精度与硬件资源利用的精细平衡。基于此权衡分析，在FPGA上实现了在线的草图处理单元（SPE），直接处理来自SPAD传感器的时间戳流。使用定制化激光雷达系统验证了192×128像素SPAD阵列上的实现效果。该工作展示了无直方图的在线深度重建，具有高保真度，有效缓解了SPAD阵列的时间戳传输瓶颈，并为未来更高像素密度的SPAD提供了可扩展方案。
原文摘要 · Abstract (English)
This study presents an efficient field-programmable gate array (FPGA) implementation of a polynomial spline function-based statistical compression algorithm designed to address the critical challenge of massive data transfer bandwidth in emerging high-spatial-resolution single-photon avalanche diode (SPAD) arrays, where data rates can reach tens of gigabytes per second. In our experiments, the proposed hardware implementation achieves a compression ratio of 512x compared with conventional histogram-based outputs, with the potential for further improvement. The algorithm is first optimized in software using fixed-point (FXP) arithmetic and look-up tables (LUTs) to eliminate explicit additions, multiplications, and non-linear operations. This enables a careful balance between accuracy and hardware resource utilization. Guided by this trade-off analysis, online sketch processing elements (SPEs) are implemented on an FPGA to directly process time-stamp streams from the SPAD sensor. The implementation is validated using a customized LiDAR setup with a 192 x 128-pixel SPAD array. This work demonstrates histogram-free online depth reconstruction with high fidelity, effectively alleviating the time-stamp transfer bottleneck of SPAD arrays and offering scalability as pixel counts continue to increase for future SPADs.
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