用多智能体强化学习实现2.5D芯片的热与布线权衡优化
TDPNavigator-Placer: Thermal- and Wirelength-Aware Chiplet Placement in 2.5D Systems Through Multi-Agent Reinforcement Learning
- 分角色智能体分别处理热设计功耗与布线长度
- 相比现有方法，热与布线平衡性能显著提升
- 适合大规模异构芯片集成的自动化布局场景
电子设备的快速发展推动了2.5D集成电路的广泛应用，系统规模扩大和芯片组异构性加剧使得高效的自动化芯片组布局变得至关重要。现有布局方法通常聚焦于最小化布线长度，或通过加权求和将多目标优化简化为单目标，难以应对相互冲突的设计需求。布线长度优化与热管理本质上存在矛盾，导致传统方法在实际部署中表现不足。为此，我们提出TDPNavigator-Placer，一种基于多智能体强化学习的新框架，依据芯片组的热设计功耗（TDP）动态优化布局。该方法将互斥目标分配给专用智能体，各智能体在统一布局范式下采用不同奖励机制和环境约束独立运作。实验表明，TDPNavigator-Placer在帕累托前沿上显著优于当前最优方法，实现了布线长度与热性能之间的更优平衡。
原文摘要 · Abstract (English)
The rapid growth of electronics has accelerated the adoption of 2.5D integrated circuits, where effective automated chiplet placement is essential as systems scale to larger and more heterogeneous chiplet assemblies. Existing placement methods typically focus on minimizing wirelength or transforming multi-objective optimization into a single objective through weighted sum, which limits their ability to handle competing design requirements. Wirelength reduction and thermal management are inherently conflicting objectives, making prior approaches inadequate for practical deployment. To address this challenge, we propose TDPNavigator-Placer, a novel multi-agent reinforcement learning framework that dynamically optimizes placement based on chiplet's thermal design power (TDP). This approach explicitly assigns these inherently conflicting objectives to specialized agents, each operating under distinct reward mechanisms and environmental constraints within a unified placement paradigm. Experimental results demonstrate that TDPNavigator-Placer delivers a significantly improved Pareto front over state-of-the-art methods, enabling more balanced trade-offs between wirelength and thermal performance.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。