用AI和加速计算让光刻更快更准更省电,首次在芯片上验证效果
Transforming Computational Lithography with AC and AI -- Faster, More Accurate, and Energy-efficient
- 用AI替代耗时的光刻模拟步骤,结合加速计算重构核心算法
- 实现57倍端到端提速,支持高精度曲边掩模和极紫外光刻
- 在芯片级验证中提升35%工艺窗口,降低19%边缘定位误差
从气候模拟到药物研发,科学计算需求近年急剧增长,受数据量增大、模型复杂度提升及仿真精度提高驱动。这一增速远超晶体管缩放速度,导致成本、能耗与碳排放不可持续。半导体制造亦面临同样挑战。计算光刻——在衍射极限下将电路图案转移到硅片上——是制造中最大的计算负载。随着进入埃米时代,器件微缩加剧,光刻变得极为复杂,需更高精度建模、复杂校正及更广解空间探索。加速计算(AC)通过大幅释放算力与功耗空间提供解决方案;人工智能则作为高保真替代模型,加速计算密集型环节。二者结合构成可持续的下一代科学计算平台。本文针对计算光刻重新设计软件栈,基于NVIDIA cuLitho重构衍射光学、计算几何、多变量优化与数据处理等核心模块,实现57倍端到端加速。算力释放后可实现更严谨的解决方案,包括曲边掩模、高数值孔径极紫外(high-NA EUV)光刻与原子级建模。我们仅投入少量释放的算力用于加入焦深补偿,显著提升工艺鲁棒性。IMEC芯片实验表明,相比传统方法,工艺窗口提升35%,边缘定位误差降低19%。这是首个在芯片尺度量化验证AC与AI光刻优势的研究。
原文摘要 · Abstract (English)
From climate science to drug discovery, scientific computing demands have surged dramatically in recent years -- driven by larger datasets, more sophisticated models, and higher simulation fidelity. This growth rate far outpaces transistor scaling, leading to unsustainably rising costs, energy consumption, and emissions. Semiconductor manufacturing is no exception. Computational lithography -- involving transferring circuitry to silicon in diffraction-limited conditions -- is the largest workload in semiconductor manufacturing. It has also grown exceptionally complex as miniaturization has advanced in the angstrom-era, requiring more accurate modeling, intricate corrections, and broader solution-space exploration. Accelerated computing (AC) offers a solution by dramatically freeing up the compute and power envelope. AI augments these gains by serving as high-fidelity surrogates for compute-intensive steps. Together, they present a sustainable, next-generation computing platform for scientific workloads. This new paradigm needs a fundamental redesign of the software stack. For computational lithography, NVIDIA cuLitho reinvents the core primitives -- diffractive optics, computational geometry, multi-variant optimization, data processing -- to achieve a transformative 57X end-to-end acceleration. Beyond dramatically faster cycles, this expanded compute envelope enables more rigorous solutions, including curvilinear masks, high-numerical aperture extreme ultraviolet (high-NA EUV) lithography, and subatomic modeling. We reinvest a small fraction of the freed-up compute to include through-focus correction for better process resilience. Silicon experiments at IMEC show significant benefits compared to conventional methods -- 35% better process window and 19% better edge placement error. This is the first quantified chip-scale demonstration of the lithography benefits of AC and AI in silicon.
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