Hexagon-MLIR让高通NPU更高效运行AI模型，支持自动编译和优化。
Hexagon-MLIR: An AI Compilation Stack For Qualcomm's Neural Processing Units (NPUs)
- 基于MLIR框架，将Triton核与PyTorch模型自动编译为NPU可执行代码。
- 生成超大核（mega-kernels），提升数据局部性，降低带宽瓶颈。
- 开源工具链，适合希望深入优化AI部署的开发者使用。
本文提出Hexagon-MLIR，一个面向高通Hexagon神经处理单元（NPU）的开源编译栈，统一支持降级Triton核与PyTorch模型。该编译器基于MLIR框架，通过一系列结构化优化传递，充分利用NPU架构特性以加速AI工作负载。它实现了从手写Triton核或PyTorch 2.0子图到二进制文件的自动化编译，加快新核的部署速度。通过摄入Triton核，系统生成能最大化利用NPU紧密耦合内存（TCM）数据局部性的超大核，减少传统库式方法中的带宽瓶颈。该项目作为商业工具链的补充，为开发者提供基于MLIR的开源编译栈，通过更灵活的方式推动AI编译能力发展。目前仍处于开发中，将持续添加更多优化与功能。
原文摘要 · Abstract (English)
In this paper, we present Hexagon-MLIR,an open-source compilation stack that targets Qualcomm Hexagon Neural Processing Unit (NPU) and provides unified support for lowering Triton kernels and PyTorch models . Built using the MLIR framework, our compiler applies a structured sequence of passes to exploit NPU architectural features to accelerate AI workloads. It enables faster deployment of new Triton kernels (hand-written or subgraphs from PyTorch 2.0), for our target by providing automated compilation from kernel to binary. By ingesting Triton kernels, we generate mega-kernels that maximize data locality in the NPU's Tightly Coupled Memory (TCM), reducing the bandwidth bottlenecks inherent in library-based approaches. This initiative complements our commercial toolchains by providing developers with an open-source MLIR-based compilation stack that gives them a path to advance AI compilation capabilities through a more flexible approach. Hexagon-MLIR is a work-in-progress, and we are continuing to add many more optimizations and capabilities in this effort.
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