用深度聚类增强边界解码网络，精准预测异质IC芯片层间应力。
Deep Clustering based Boundary-Decoder Net for Inter and Intra Layer Stress Prediction of Heterogeneous Integrated IC Chip
- 结合边界解码与深度聚类，从材料参数推断应力分布。
- 在1825张仿真应力图上，训练与测试误差均显著低于对比方法。
- 适合集成电路热应力分析、可靠性设计的研究者使用。
3D异质集成电路封装在极端温变下易产生高应力，主要集中在不同材料界面。本文利用基于深度生成模型（DGM）的潜在空间表示来研究应力图像。现有大部分DGM方法为无监督学习，依赖图像配对进行训练。本文采用一种新型边界解码（BD）网络，结合边界条件与图像配对实现应力建模。边界网络将材料参数映射至与图像共享的潜在空间。由于该设定维度上病态，我们进一步引入深度聚类。为评估性能，我们构建了包含1825张应力图像的IC芯片仿真数据集，并对比了多种BD网络变体及基线方法。结果表明，所提方法在训练与测试误差降低方面均优于所有对比方法。
原文摘要 · Abstract (English)
High stress occurs when 3D heterogeneous IC packages are subjected to thermal cycling at extreme temperatures. Stress mainly occurs at the interface between different materials. We investigate stress image using latent space representation which is based on using deep generative model (DGM). However, most DGM approaches are unsupervised, meaning they resort to image pairing (input and output) to train DGM. Instead, we rely on a recent boundary-decoder (BD) net, which uses boundary condition and image pairing for stress modeling. The boundary net maps material parameters to the latent space co-shared by its image counterpart. Because such a setup is dimensionally wise ill-posed, we further couple BD net with deep clustering. To access the performance of our proposed method, we simulate an IC chip dataset comprising of 1825 stress images. We compare our new approach using variants of BD net as well as a baseline approach. We show that our approach is able to outperform all the comparison in terms of train and test error reduction.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。