提出可运行时重构的多精度乘法阵列，提升神经网络加速器效率。
Bitwise Systolic Array Architecture for Runtime-Reconfigurable Multi-precision Quantized Multiplication on Hardware Accelerators
- 设计支持运行时多精度重构的位级脉动阵列架构。
- 在混合精度模型上实现1.32至3.57倍加速，时钟频率达250MHz。
- 适合需要动态精度调整的边缘设备神经网络部署。
神经网络加速器已广泛应用于边缘设备，执行目标跟踪、图像识别等复杂任务。现有轻量级加速器设计通过量化技术降低硬件资源消耗，但低精度会导致推理准确率显著下降。因此，混合精度量化成为替代方案，通过在不同网络层使用不同精度，在资源消耗与准确率间取得平衡。然而，传统硬件乘法设计无法在运行时支持多精度量化神经网络（QNN）的精度切换。为此，本文提出一种支持运行时重构的多精度多通道位级脉动阵列架构，用于QNN加速器。我们在Ultra96 FPGA平台上实现了该设计并进行了评估。结果表明，该方法在推理混合精度模型时可获得1.3185至3.5671倍的加速比，关键路径延迟更短，支持高达250MHz的时钟频率。
原文摘要 · Abstract (English)
Neural network accelerators have been widely applied to edge devices for complex tasks like object tracking, image recognition, etc. Previous works have explored the quantization technologies in related lightweight accelerator designs to reduce hardware resource consumption. However, low precision leads to high accuracy loss in inference. Therefore, mixed-precision quantization becomes an alternative solution by applying different precision in different layers to trade off resource consumption and accuracy. Because regular designs for multiplication on hardware cannot support the precision reconfiguration for a multi-precision Quantized Neural Network (QNN) model in runtime, we propose a runtime reconfigurable multi-precision multi-channel bitwise systolic array design for QNN accelerators. We have implemented and evaluated our work on the Ultra96 FPGA platform. Results show that our work can achieve 1.3185 to 3.5671 times speedup in inferring mixed-precision models and has less critical path delay, supporting a higher clock frequency (250MHz).
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