TinyIceNet在卫星上实现低功耗海冰分割,实时处理雷达图像。
TinyIceNet: Low-Power SAR Sea Ice Segmentation for On-Board FPGA Inference
- 专为卫星硬件设计轻量模型,结合雷达特性与低精度量化。
- 在AI4Arctic数据集上达75.216% F1分数,能耗比全精度GPU降低2倍。
- 适合极地导航、星载智能处理及边缘计算场景的科研与工程应用。
准确的海冰制图对极地航行安全至关重要,因冰况变化迅速,需及时可靠信息。尽管哨兵-1合成孔径雷达(SAR)能提供高分辨率、全天候海冰观测,但传统地面处理受限于下行链路带宽、延迟和传输大量原始数据的能耗。星载处理通过在卫星载荷中集成专用推理芯片,可实现轨道上即时生成可用海冰产品,带来变革。本文提出TinyIceNet,一种面向双极化哨兵-1 SAR影像的星载海冰阶段(SOD)分割紧凑语义分割网络,在严格硬件与功耗约束下协同设计。模型在AI4Arctic数据集上训练,融合雷达感知的结构简化与低精度量化,以平衡精度与效率。通过高层次综合在Xilinx Zynq UltraScale+ FPGA平台部署,实现近实时推理,显著降低能耗。实验表明,TinyIceNet在SOD分割上达到75.216% F1分数,相比全精度GPU基线能耗降低2倍,凸显芯片级软硬件协同设计在未来的星载与边缘人工智能系统中的潜力。
原文摘要 · Abstract (English)
Accurate sea ice mapping is essential for safe maritime navigation in polar regions, where rapidly changing ice conditions require timely and reliable information. While Sentinel-1 Synthetic Aperture Radar (SAR) provides high-resolution, all-weather observations of sea ice, conventional ground-based processing is limited by downlink bandwidth, latency, and energy costs associated with transmitting large volumes of raw data. On-board processing, enabled by dedicated inference chips integrated directly within the satellite payload, offers a transformative alternative by generating actionable sea ice products in orbit. In this context, we present TinyIceNet, a compact semantic segmentation network co-designed for on-board Stage of Development (SOD) mapping from dual-polarized Sentinel-1 SAR imagery under strict hardware and power constraints. Trained on the AI4Arctic dataset, TinyIceNet combines SAR-aware architectural simplifications with low-precision quantization to balance accuracy and efficiency. The model is synthesized using High-Level Synthesis and deployed on a Xilinx Zynq UltraScale+ FPGA platform, demonstrating near-real-time inference with significantly reduced energy consumption. Experimental results show that TinyIceNet achieves 75.216% F1 score on SOD segmentation while reducing energy consumption by 2x compared to full-precision GPU baselines, underscoring the potential of chip-level hardware-algorithm co-design for future spaceborne and edge AI systems.
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