AI自主设计出1.48GHz可运行Linux的RISC-V核，12小时完成全流程。
Design Conductor: An agent autonomously builds a 1.5 GHz Linux-capable RISC-V CPU
- AI从219词需求文档出发，自主完成从架构到版图的全流程芯片设计。
- 设计的VerCore核在ASAP7工艺下达1.48GHz，CoreMark得分3261，相当于2011年酷睿赛扬。
- 首次实现完全自主生成可流片的完整CPU，适合关注AI造芯未来的研究者。
Design Conductor（DC）是一个自主代理，利用前沿大模型能力实现半导体从概念到验证通过、可流片的GDSII版图的端到端构建。在12小时内完全自主地，DC基于一份219词的需求文档，成功构建了多个完整RISC-V CPU微架构变体（我们称为VerCore），其在ASAP7工艺下时钟频率达到1.48 GHz（rv32i-zmmul），并实现了3261的CoreMark得分。历史对比显示，这大致等同于2011年中段发布的英特尔酷睿赛扬SU2300（运行频率1.2 GHz）。据我们所知，这是首个从规格到GDSII全流程由自主代理完成的完整可运行CPU。本文首先介绍DC的设计及其核心组件，随后描述构建VerCore的方法论，包括RTL实现、测试平台搭建、前端调试、时序优化以达成时序收敛，并与后端工具交互。接着分析所得VerCore的关键特性。最后，探讨前沿模型如何进一步优化以支持此类应用，并总结关于未来芯片制造方式的启示。
原文摘要 · Abstract (English)
Design Conductor (DC) is an autonomous agent which applies the capabilities of frontier models to build semiconductors end-to-end -- that is, from concept to verified, tape-out ready GDSII (layout CAD file). In 12 hours and fully autonomously, DC was able to build several micro-architecture variations of a complete RISC-V CPU (which we dub VerCore) that meet timing at 1.48 GHz (rv32i-zmmul; using the ASAP7 PDK), starting from a 219-word requirements document. The VerCore achieves a CoreMark score of 3261. For historical context, this is roughly equivalent to an Intel Celeron SU2300 from mid-2011 (which ran at 1.2 GHz). To our knowledge, this is the first time an autonomous agent has built a complete, working CPU from spec to GDSII. This report is organized as follows. We first review DC's design and its key components. We then describe the methodology that DC followed to build VerCore -- including RTL implementation, testbench implementation, frontend debugging, optimization to achieve timing closure, and interacting with backend tools. We review the key characteristics of the resulting VerCore. Finally, we highlight how frontier models could improve to better enable this application, and our lessons learned as to how chips will be built in the future enabled by the capabilities of systems like DC.
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