用多智能体框架让AI自动生成并调试硬件代码，更准更省资源。
SiliconMind-V1: Multi-Agent Distillation and Debug-Reasoning Workflows for Verilog Code Generation
- 设计多智能体协作生成和验证Verilog代码，支持本地微调
- 在三个基准上功能正确率超当前最优模型，训练成本更低
- 适合芯片设计自动化、AI辅助硬件开发的开发者使用
大语言模型（LLMs）在自动编写Verilog代码方面展现出潜力，但现有方法多关注语法正确性，依赖商用模型或外部验证工具，带来成本高、数据隐私风险及功能正确性保障不足的问题。本文提出一种统一的多智能体推理式训练数据生成框架，集成测试平台驱动的验证机制，使本地微调后的LLM——SiliconMind-V1，可通过测试时扩展实现代码的迭代生成、测试与调试。在代表性的基准（VerilogEval-v2、RTLLM-v2 和 CVDP）上的实验表明，该方法在功能正确性上优于当前最优模型QiMeng-CodeV-R1，同时使用更少的训练资源。
原文摘要 · Abstract (English)
Large language models (LLMs) have recently emerged as a promising approach for automating Verilog code generation; however, existing methods primarily emphasize syntactic correctness and often rely on commercial models or external verification tools, which introduces concerns regarding cost, data privacy, and limited guarantees of functional correctness. This work proposes a unified multi-agent framework for reasoning-oriented training data generation with integrated testbench-driven verification, enabling locally fine-tuned LLMs, SiliconMind-V1, to iteratively generate, test, and debug Register-Transfer Level (RTL) designs through test-time scaling. Experimental results on representative benchmarks (VerilogEval-v2, RTLLM-v2, and CVDP) demonstrate that the proposed approach outperforms the state-of-the-art QiMeng-CodeV-R1 in functional correctness while using fewer training resources.
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