针对FPGA上CNN推理的数据率问题，提出自适应加速架构提升资源利用率。
Data-Rate-Aware High-Speed CNN Inference on FPGAs
- 根据各层数据率动态调整硬件配置，保持流水线持续运行。
- 相比之前设计，算术资源减少显著，支持复杂CNN在单FPGA上高效运行。
- 适合需要高吞吐、低延迟且资源受限的边缘部署场景。
基于数据流的FPGA CNN加速器通过将每层计算直接映射到相应硬件单元，实现低延迟和高吞吐。然而，池化和步幅卷积等操作会降低输出数据率，严重影响后续层的数据流速率，导致全展开设计中硬件利用率下降。尽管已有研究提出数据率感知的逐层适配方法，但如何确定最优实现仍具挑战。本文提出一种面向多像素处理的数据率感知CNN加速架构。基于现有分析模型，该方法进行设计空间探索，识别能提升硬件利用率与资源效率的配置，同时保持数据连续流动，确保所有硬件单元持续工作。实验结果表明，相比先前设计，算术资源显著减少，可在单个FPGA上高效实现多种数据率下的复杂CNN模型。
原文摘要 · Abstract (English)
Dataflow-based CNN accelerators on FPGAs achieve low latency and high throughput by mapping computations of each layer directly to corresponding hardware units. However, layers such as pooling and strided convolutions reduce the data at their output with respect to their input, strongly effecting the data rate of the following layers. This leads to underutilization in fully unrolled designs. While prior work introduced data-rate-aware layer-wise adaptation, determining the most efficient implementation remains challenging. This paper presents a data-rate-aware CNN accelerator architecture for multi-pixel processing. Building on existing analytical models, the proposed method performs design-space exploration to identify configurations that improve hardware utilization and resource efficiency while preserving continuous flow of data, keeping all hardware units busy. Experimental results show substantial reductions in arithmetic resources compared to previous designs, enabling efficient implementation of complex CNNs on a single FPGA across a wide range of data rates.
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