为高性能AI数据流设计内核级缓冲协调框架，解决内存管理痛点。
The DMA Streaming Framework: Kernel-Level Buffer Orchestration for High-Performance AI Data Paths
- 在内核层实现缓冲区全生命周期管理与跨设备共享
- 支持NUMA感知分配，在跨节点场景下降低延迟15%以上
- 适合需要低延迟、高可靠数据传输的分布式AI推理系统
AI传输库虽能高效搬运字节，但普遍假设缓冲区已正确分配、放置、共享、注册，并在完成与释放压力下安全。本文提出dmaplane，一个Linux内核模块，将这一缺失的缓冲区协调层显式化。dmaplane通过 /dev/dmaplane 提供稳定内核UAPI，集成基于环形队列的命令通道、DMA缓冲区生命周期管理、dma-buf跨设备共享、内核空间RDMA引擎、NUMA感知分配与验证、基于信用的流量控制、低开销可观测性，以及通过PCIe BAR绑定实现的GPU内存集成。我们通过测量DRAM规模下的跨节点NUMA惩罚、持续RDMA负载下的完成安全流量控制，以及GPU BAR映射层级与cudaMemcpy的对比，评估协调机制敏感性。还演示了端到端分离式推理：使用RDMA WRITE WITH IMMEDIATE在两台机器间传输KV缓存块，并在接收端重构张量视图。所有RDMA测试采用Soft-RoCE；通过构造区分实测结果与平台无关属性。
原文摘要 · Abstract (English)
AI transport libraries move bytes efficiently, but they commonly assume that buffers are already correctly allocated, placed, shared, registered, and safe under completion and teardown pressure. This paper presents dmaplane, a Linux kernel module that makes this missing layer explicit as buffer orchestration. dmaplane exposes a stable kernel UAPI via /dev/dmaplane and composes ring-based command channels, DMA buffer lifecycle management, dma-buf export for cross-device sharing, a kernel-space RDMA engine, NUMA-aware allocation and verification, credit-based flow control, low-overhead observability, and GPU memory integration via PCIe BAR pinning. We evaluate orchestration sensitivity with measurements of NUMA cross-node penalties at DRAM scale, completion-safe flow control under sustained RDMA load, and GPU BAR mapping tiers versus cudaMemcpy. We also demonstrate end-to-end disaggregated inference by transferring KV-cache chunks between two machines using RDMA WRITE WITH IMMEDIATE and reconstructing tensor views on the receiver. RDMA measurements use Soft-RoCE; we distinguish measured results from provider-independent properties by construction.
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