为JPEG XS的帧内预测搜索设计高效FPGA架构，提升硬件部署可行性。
An FPGA Implementation of Displacement Vector Search for Intra Pattern Copy in JPEG XS
- 采用流水线结构与优化内存布局，匹配IPC计算特性。
- 实现38.3兆像素/秒吞吐量，功耗仅277毫瓦。
- 适合低延迟图像压缩系统，可推广至其他预测编码场景。
近期，JPEG XS标准中的帧内模式复制（IPC）工具在减少屏幕内容空间冗余方面取得进展，其通过小波域帧内补偿预测实现。核心模块为位移向量（DV）搜索，旨在寻找最优参考偏移，但该过程计算复杂度高，制约实际硬件部署。本文提出一种高效的流水线化FPGA架构设计用于DV搜索模块，并引入基于IPC计算特性与数据重用模式的优化内存组织以提升性能。实验结果表明，所提架构在277 mW功耗下实现38.3 Mpixels/s的吞吐量，验证了其在IPC及其他预测编码工具中实际硬件部署的可行性，为ASIC设计提供良好基础。
原文摘要 · Abstract (English)
Recently, progress has been made on the Intra Pattern Copy (IPC) tool for JPEG XS, an image compression standard designed for low-latency and low-complexity coding. IPC performs wavelet-domain intra compensation predictions to reduce spatial redundancy in screen content. A key module of IPC is the displacement vector (DV) search, which aims to solve the optimal prediction reference offset. However, the DV search process is computationally intensive, posing challenges for practical hardware deployment. In this paper, we propose an efficient pipelined FPGA architecture design for the DV search module to promote the practical deployment of IPC. Optimized memory organization, which leverages the IPC computational characteristics and data inherent reuse patterns, is further introduced to enhance the performance. Experimental results show that our proposed architecture achieves a throughput of 38.3 Mpixels/s with a power consumption of 277 mW, demonstrating its feasibility for practical hardware implementation in IPC and other predictive coding tools, and providing a promising foundation for ASIC deployment.
Thank you to arXiv for use of its open access interoperability. PaperDance 不是 arXiv 官方产品；中文卡片由大模型生成，请以原文为准。