用异构图统一电路与布局，提前精准预测芯片布线拥塞。
VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification
- 构建融合电路元件与空间网格的异构图，建模逻辑与物理的交互。
- 在ISPD2015等工业基准上，预测准确率和相关性均达顶尖水平。
- 适合芯片验证、EDA工具研发人员快速评估布线风险。
随着超大规模集成电路（VLSI）设计规模与复杂度持续增长，版图验证已成为现代电子设计自动化（EDA）流程的核心挑战。实际中，拥塞只有在详细布线后才能准确识别，导致传统验证耗时且成本高昂。为此，学习方法被用于早期拥塞预测，以减少布线迭代次数。然而，现有方法虽融合网表连接与版图特征，但常以松散方式建模二者关系，且主要输出数值拥塞估计。本文提出VeriHGN，一个基于增强异构图的验证框架，将电路单元与空间网格统一为单一关系表示，更真实地捕捉逻辑意图与物理实现间的交互。在工业基准ISPD2015、CircuitNet-N14与CircuitNet-N28上的实验表明，VeriHGN在预测精度与相关性指标上达到或接近当前最优水平。
原文摘要 · Abstract (English)
As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate that VeriHGN achieves the best or near-best performance over state-of-the-art methods in prediction accuracy and correlation metrics.
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