通过时间并行性加速LSTM自编码器，实现低延迟高能效的异常检测。
Exploiting temporal parallelism for LSTM Autoencoder acceleration on FPGA
- 设计数据流架构，同时处理序列中不同时间步的多层LSTM计算
- 相比CPU最高提速79.6倍，功耗降低1722倍，深度扩展性更优
- 适合实时、低功耗场景下的时间序列异常检测系统部署
循环神经网络在序列数据处理中至关重要。长短期记忆自编码器（LSTM-AE）在时间序列无监督异常检测中表现优异，但固有的时序依赖限制了并行计算。现有FPGA加速工作多集中于单层LSTM优化。本文提出一种新型FPGA加速器，采用数据流架构，利用时间并行性实现序列中不同时间步的多层并发处理。在Zynq UltraScale+ MPSoC FPGA上对四种不同宽度与深度的LSTM-AE模型进行评估，结果表明：相比CPU（Intel Xeon Gold 5218R）和GPU（NVIDIA V100），本方案在延迟上最高提速79.6倍（对比CPU）、18.2倍（对比GPU），每时间步能耗降低最高达1722倍（对比CPU）、59.3倍（对比GPU）。优异的深度可扩展性进一步凸显该方法在高性能、实时、低功耗的LSTM-AE异常检测中的应用潜力。
原文摘要 · Abstract (English)
Recurrent Neural Networks (RNNs) are vital for sequential data processing. Long Short-Term Memory Autoencoders (LSTM-AEs) are particularly effective for unsupervised anomaly detection in time-series data. However, inherent sequential dependencies limit parallel computation. While previous work has explored FPGA-based acceleration for LSTM networks, efforts have typically focused on optimizing a single LSTM layer at a time. We introduce a novel FPGA-based accelerator using a dataflow architecture that exploits temporal parallelism for concurrent multi-layer processing of different timesteps within sequences. Experimental evaluations on four representative LSTM-AE models with varying widths and depths, implemented on a Zynq UltraScale+ MPSoC FPGA, demonstrate significant advantages over CPU (Intel Xeon Gold 5218R) and GPU (NVIDIA V100) implementations. Our accelerator achieves latency speedups up to 79.6x vs. CPU and 18.2x vs. GPU, alongside energy-per-timestep reductions of up to 1722x vs. CPU and 59.3x vs. GPU. These results, including superior network depth scalability, highlight our approach's potential for high-performance, real-time, power-efficient LSTM-AE-based anomaly detection on FPGAs.
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