FPGA加速神经网络，提升航天器本地推理性能与能效。
Evaluating Four FPGA-accelerated Space Use Cases based on Neural Network Algorithms for On-board Inference
- 用FPGA在ZCU104板上实现NN推理，对比Vitis AI与HLS方案。
- 最高推理速度达CPU的34.16倍，功耗降至1.5-6.75W。
- 适合需低延迟、低功耗推理的深空探测与星载智能任务。
空间任务越来越多地部署高保真传感器，产生的数据量已超过星载缓冲和下行链路容量。本文基于AMD ZCU104平台，评估了神经网络（NN）在四种太空应用场景中采用FPGA加速的效果。使用Vitis AI（AMD DPU）和Vitis HLS实现推理，量化吞吐量与能耗，并揭示部署相关的工具链与架构限制。Vitis AI相比嵌入式ARM CPU基线最高可实现34.16倍的推理速率提升；自定义HLS设计最高达5.4倍加速，且支持DPU不支持的操作符（如sigmoid、3D层）。这些实现的MPSoC推理功耗为1.5–6.75 W，所有场景下均低于CPU执行的单位推理能耗。结果表明，神经网络的FPGA加速可实现星载数据过滤、压缩与事件检测，缓解未来任务的下行压力。
原文摘要 · Abstract (English)
Space missions increasingly deploy high-fidelity sensors that produce data volumes exceeding onboard buffering and downlink capacity. This work evaluates FPGA acceleration of neural networks (NNs) across four space use cases on the AMD ZCU104 board. We use Vitis AI (AMD DPU) and Vitis HLS to implement inference, quantify throughput and energy, and expose toolchain and architectural constraints relevant to deployment. Vitis AI achieves up to 34.16$\times$ higher inference rate than the embedded ARM CPU baseline, while custom HLS designs reach up to 5.4$\times$ speedup and add support for operators (e.g., sigmoids, 3D layers) absent in the DPU. For these implementations, measured MPSoC inference power spans 1.5-6.75 W, reducing energy per inference versus CPU execution in all use cases. These results show that NN FPGA acceleration can enable onboard filtering, compression, and event detection, easing downlink pressure in future missions.
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