用RTL引导生成代码，提升硬件断言自动生成效果
QiMeng-CodeV-SVA: Training Specialized LLMs for Hardware Assertion Generation via RTL-Grounded Bidirectional Data Synthesis
- 基于RTL代码生成真实场景的断言数据，解决训练数据少问题
- 双向翻译筛选数据，提升自然语言到断言的匹配准确率
- 模型在多个测试集上超越GPT-5等大模型，适合硬件验证人员
系统Verilog断言（SVAs）对硬件验证至关重要。现有研究尝试用通用大模型将自然语言属性转换为SVAs（NL2SVA），但因数据匮乏表现不佳。本文提出一种数据合成框架，解决两大挑战：高质量真实SVA语料稀缺、以及难以判断自然语言与SVA语义是否等价。针对前者，利用大规模开源RTL代码引导大模型生成真实场景的SVAs；针对后者，采用双向翻译作为数据筛选方法。基于合成数据，我们训练出CodeV-SVA系列断言生成模型。其中，CodeV-SVA-14B在NL2SVA-Human任务上达到75.8%的Func.@1，在NL2SVA-Machine上达到84.0%，性能媲美甚至超过GPT-5和DeepSeek-R1等先进模型。
原文摘要 · Abstract (English)
SystemVerilog Assertions (SVAs) are crucial for hardware verification. Recent studies leverage general-purpose LLMs to translate natural language properties to SVAs (NL2SVA), but they perform poorly due to limited data. We propose a data synthesis framework to tackle two challenges: the scarcity of high-quality real-world SVA corpora and the lack of reliable methods to determine NL-SVA semantic equivalence. For the former, large-scale open-source RTLs are used to guide LLMs to generate real-world SVAs; for the latter, bidirectional translation serves as a data selection method. With the synthesized data, we train CodeV-SVA, a series of SVA generation models. Notably, CodeV-SVA-14B achieves 75.8% on NL2SVA-Human and 84.0% on NL2SVA-Machine in Func.@1, matching or exceeding advanced LLMs like GPT-5 and DeepSeek-R1.
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