用符号规划提升硬件代码生成与摘要质量
SYMDIREC: A Neuro-Symbolic Divide-Retrieve-Conquer Framework for Enhanced RTL Synthesis and Summarization
- 将硬件任务拆解为符号子目标，结合检索与大模型推理
- 合成任务通过率提升20%，摘要ROUGE-L提高15-20%
- 无需微调模型，支持Verilog和VHDL
寄存器传输级（RTL）综合与摘要在硬件设计自动化中至关重要，但大型语言模型（LLM）因严格HDL语法、监督有限及与自然语言对齐不足而面临挑战。现有提示与检索增强生成（RAG）方法未引入符号规划，导致结构精度受限。我们提出SYMDIREC，一种神经符号框架，将RTL任务分解为符号子目标，通过微调检索器获取相关代码，并利用大模型推理组装验证输出。该框架无需对LLM进行微调，即可支持Verilog和VHDL。在合成任务上，其Pass@1率比提示和RAG基线高出约20%；在摘要任务上，ROUGE-L提升15-20%，证明了符号引导在RTL任务中的优势。
原文摘要 · Abstract (English)
Register-Transfer Level (RTL) synthesis and summarization are central to hardware design automation but remain challenging for Large Language Models (LLMs) due to rigid HDL syntax, limited supervision, and weak alignment with natural language. Existing prompting and retrieval-augmented generation (RAG) methods have not incorporated symbolic planning, limiting their structural precision. We introduce SYMDIREC, a neuro-symbolic framework that decomposes RTL tasks into symbolic subgoals, retrieves relevant code via a fine-tuned retriever, and assembles verified outputs through LLM reasoning. Supporting both Verilog and VHDL without LLM fine-tuning, SYMDIREC achieves ~20% higher Pass@1 rates for synthesis and 15-20% ROUGE-L improvements for summarization over prompting and RAG baselines, demonstrating the benefits of symbolic guidance in RTL tasks.
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