将KAN网络的B样条参数量化至2-3比特，大幅降低计算开销且不损失精度。
KANtize: Exploring Low-bit Quantization of Kolmogorov-Arnold Networks for Efficient Inference
- 用低比特量化替代传统递归B样条计算，提升推理效率
- 2-3比特量化后模型精度几乎不变，计算量减少50倍
- 适合硬件部署，尤其在FPGA和ASIC上显著提升速度与能效
Kolmogorov-Arnold Networks（KANs）因其参数高效性和可解释性，被认为可能超越多层感知机（MLPs）。KANs使用可学习的非线性激活函数，通常为分段多项式函数（如B样条），其参数为B样条系数。然而，推理时求解B样条函数会增加计算复杂度。传统量化通过降低参数与激活值精度来缓解此问题，但对低于8比特的量化在KAN上的效果仍不明确。本文研究低比特量化对KAN的影响，发现B样条可被量化至2-3比特而几乎不影响精度，显著降低计算复杂度。为此，我们提出用低比特预计算查表替代递归B样条算法，进一步优化硬件效率。例如，ResKAN18在不损失精度的情况下实现50倍的BitOps减少；8比特查表使GPU推理加速最高达2.9倍；在FPGA流水线加速器上，将样条表精度从8位降至3位，资源占用减少36%，时钟频率提升50%，加速比提高1.24倍；在28nm FD-SOI ASIC上，将样条位宽从16位降至3位，面积减少72%，最大频率提高50%。
原文摘要 · Abstract (English)
Kolmogorov-Arnold Networks (KANs) have gained attention for their potential to outperform Multi-Layer Perceptrons (MLPs) in terms of parameter efficiency and interpretability. Unlike traditional MLPs, KANs use learnable non-linear activation functions, typically spline functions, expressed as linear combinations of basis splines (B-splines). B-spline coefficients serve as the model's learnable parameters. However, evaluating these spline functions increases computational complexity during inference. Conventional quantization reduces this complexity by lowering the numerical precision of parameters and activations. However, the impact of quantization on KANs, and especially its effectiveness in reducing computational complexity, is largely unexplored, particularly for quantization levels below 8 bits. The study investigates the impact of low-bit quantization on KANs and its impact on computational complexity and hardware efficiency. Results show that B-splines can be quantized to 2-3 bits with negligible loss in accuracy, significantly reducing computational complexity. Hence, we investigate the potential of using low-bit quantized precomputed tables as a replacement for the recursive B-spline algorithm. This approach aims to further reduce the computational complexity of KANs and enhance hardware efficiency while maintaining accuracy. For example, ResKAN18 achieves a 50x reduction in BitOps without loss of accuracy using low-bit-quantized B-spline tables. Additionally, precomputed 8-bit lookup tables improve GPU inference speedup by up to 2.9x, while on FPGA-based systolic-array accelerators, reducing B-spline table precision from 8 to 3 bits cuts resource usage by 36%, increases clock frequency by 50%, and enhances speedup by 1.24x. On a 28nm FD-SOI ASIC, reducing the B-spline bit-width from 16 to 3 bits achieves 72% area reduction and 50% higher maximum frequency.
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